MC68HC705J1ACDW Freescale Semiconductor, MC68HC705J1ACDW Datasheet - Page 93

IC MCU 4MHZ 1.2K OTP 20-SOIC

MC68HC705J1ACDW

Manufacturer Part Number
MC68HC705J1ACDW
Description
IC MCU 4MHZ 1.2K OTP 20-SOIC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705J1ACDW

Core Processor
HC05
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
14
Program Memory Size
1.2KB (1.2K x 8)
Program Memory Type
OTP
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Connectivity
-

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6.4.2 Data Direction Register B
MC68HC705J1A — Rev. 4.0
NOTE:
Address:
Data direction register B (DDRB) determines whether each port B pin is
an input or an output.
DDRB[5:0] — Data Direction Register B Bits
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 6-8
Reset:
Read:
Write:
These read/write bits control port B data direction. Reset clears
DDRB[5:0], configuring all port B pins as inputs.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
READ DDRB
WRITE DDRB
WRITE PORTB
READ PORTB
WRITE PDRB
$0005
Bit 7
0
0
Parallel Input/Output (I/O) Ports
Figure 6-7. Data Direction Register B (DDRB)
shows the I/O logic of port B.
Go to: www.freescale.com
= Unimplemented
RESET
6
0
0
Figure 6-8. Port B I/O Circuitry
DDRB5
5
0
DDRBx
PDRBx
PBx
DDRB4
4
0
DDRB3
3
0
SWPDI
Parallel Input/Output (I/O) Ports
DDRB2
2
0
DDRB1
100- A
PULLDOWN
1
0
Technical Data
PBx
DDRB0
Bit 0
Port B
0

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