MC68HC16Z1CPV25 Freescale Semiconductor, MC68HC16Z1CPV25 Datasheet - Page 176
![IC MPU 1K RAM 25MHZ 144-LQFP](/photos/6/76/67683/375-144-tqfp_sml.jpg)
MC68HC16Z1CPV25
Manufacturer Part Number
MC68HC16Z1CPV25
Description
IC MPU 1K RAM 25MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HC16r
Datasheet
1.MC68HC16Z1VEH16.pdf
(500 pages)
Specifications of MC68HC16Z1CPV25
Core Processor
CPU16
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
Q1141110
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5.10 Parallel Input/Output Ports
5.10.1 Pin Assignment Registers
5.10.2 Data Direction Registers
5-70
However, the internal pull-up driver can be overcome by bus loading effects. To en-
sure a particular configuration out of reset, use an active device to put DATA0 in a
known state during reset.
The base address field in the boot chip-select base address register CSBARBT has a
reset value of all zeros, so that when the initial access to address $000000 is made,
an address match occurs, and the CSBOOT signal is asserted. The block size field in
CSBARBT has a reset value of 512 Kbytes.
Sixteen SIM pins can be configured for general-purpose discrete input and output. Al-
though these pins are organized into two ports, port E and port F, function assignment
is by individual pin. PE3 is not connected to a pin. PE3 returns zero when read and
writes have no effect. Pin assignment registers, data direction registers, and data reg-
isters are used to implement discrete I/O.
Bits in the port E and port F pin assignment registers (PEPAR and PFPAR) control the
functions of the pins on each port. Any bit set to one defines the corresponding pin as
a bus control signal. Any bit cleared to zero defines the corresponding pin as an I/O
pin. PEPA3 returns one when read, and writes have no effect.
Bits in the port E and port F data direction registers (DDRE and DDRF) control the di-
rection of the pin drivers when the pins are configured as I/O. Any bit in a register set
to one configures the corresponding pin as an output. Any bit in a register cleared to
zero configures the corresponding pin as an input. These registers can be read or writ-
ten at any time. DDE3 returns zero when read. Writes have no effect.
Table 5-26 CSBOOT Base and Option Register Reset Values
NOTES:
Freescale Semiconductor, Inc.
Async/sync mode
Upper/lower byte
1. These fields are not used unless “Address space” is
Address space
For More Information On This Product,
Base address
set to CPU space.
Read/write
Autovector
Block size
DSACK
AS/DS
Fields
SYSTEM INTEGRATION MODULE
IPL
1
Go to: www.freescale.com
Interrupt vector externally
Asynchronous mode
Table 5-26
Supervisor space
Reset Values
13 wait states
Both bytes
Read/write
512 Kbyte
Any level
$000000
AS
shows CSBOOT reset values.
M68HC16 Z SERIES
USER’S MANUAL
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