MC68HC16Z1CPV25 Freescale Semiconductor, MC68HC16Z1CPV25 Datasheet - Page 410

• Manufacturer Part Number: MC68HC16Z1CPV25
• Description: IC MPU 1K RAM 25MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CPV25

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: Q1141110

D.5.6 ADC Status Register
ADCSTAT — ADC Status Register
SCF — Sequence Complete Flag
CCTR[2:0] — Conversion Counter
CCF[7:0] — Conversion Complete Flags
D.5.7 Right Justified, Unsigned Result Register
D.5.8 Left Justified, Signed Result Register
D-36
RJURR — Right-Justified, Unsigned Result Register
LJSRR — Left Justified, Signed Result Register
SCF
8/10
15
0
15
15
RESET:
ADCSTAT contains information related to the status of a conversion sequence.
SCF is set at the end of the conversion sequence when SCAN is cleared, and at the
end of the first conversion sequence when SCAN is set. SCF is cleared when ADCTL1
is written and a new conversion sequence begins.
This field reflects the contents of the conversion counter pointer in either four or eight
count conversion sequence. The value corresponds to the number of the next result
register to be written, and thus indicates which channel is being converted.
Each bit in this field corresponds to an A/D result register (for example, CCF7 to
RSLT7). A bit is set when conversion for the corresponding channel is complete, and
remains set until the associated result register is read.
Conversion result is unsigned right-justified data. Bits [9:0] are used for 10-bit resolu-
tion. For 8-bit conversions, bits [7:0] contain data and bits [9:8] are zero. Bits [15:10]
always return zero when read.
Conversion result is signed left-justified data. Bits [15:6] are used for 10-bit resolution.
For 8-bit conversions, bits [15:8] contain data and bits [7:6] are zero. Although the ADC
is unipolar, it is assumed that the zero point is halfway between low and high reference
when this format is used (V
put, bit 15 = 1. Bits [5:0] always return zero when read.
0 = Sequence not complete
1 = Sequence complete
8/10
14
14
8/10
13
NOT USED
13
NOT USED
8/10
12
12
Freescale Semiconductor, Inc.
8/10
11
11
For More Information On This Product,
8/10
10
10
10
0
RH
Go to: www.freescale.com
CCTR[2:0]
– V
REGISTER SUMMARY
8/10
10
9
0
9
9
RL
/2). For positive input, bit 15 = 0. For negative in-
8/10
10
8
0
8
8
8/10
10
7
0
7
7
8/10
10
6
0
6
6
8/10
5
5
5
0
8/10
4
4
0
CCF[7:0]
$YFF710–$YFF71F
$YFF720–$YFF72F
8/10
NOT USED
3
3
0
M68HC16 Z SERIES
USER’S MANUAL
8/10
2
2
0
$YFF70E
8/10
1
1
0
8/10
0
0
0
0