MC68HC16Z1CPV25 Freescale Semiconductor, MC68HC16Z1CPV25 Datasheet - Page 249

• Manufacturer Part Number: MC68HC16Z1CPV25
• Description: IC MPU 1K RAM 25MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CPV25

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: Q1141110

10.3.4.1 CPHA = 0 Transfer Format
M68HC16 Z SERIES
USER’S MANUAL
SCK (CPOL = 0)
SCK (CPOL = 1)
(FROM MASTER)
(FROM SLAVE)
SS (TO SLAVE)
MISO
Figure 10-3
equals zero. Two waveforms are shown for SCK: one for CPOL equal to zero and an-
other for CPOL equal to one. The diagram may be interpreted as a master or slave
timing diagram since the SCK, MISO and MOSI pins are directly connected between
the master and the slave. The MISO signal shown is the output from the slave and the
MOSI signal shown is the output from the master. The SS line is the chip-select input
to the slave.
For a master, writing to the SPDR initiates the transfer. For a slave, the falling edge of
SS indicates the start of a transfer. The SCK signal remains inactive for the first half
of the first SCK cycle. Data is latched on the first and each succeeding odd clock edge,
and the SPI shift register is left-shifted on the second and succeeding even clock edg-
es. SPIF is set at the end of the eighth SCK cycle.
When CPHA equals zero, the SS line must be negated and reasserted between each
successive serial byte. If the slave writes data to the SPI data register while SS is as-
serted (low), a write collision error results. To avoid this problem, the slave should read
bit three of PORTMCP, which indicates the state of the SS pin, before writing to the
SPDR again.
MOSI
(FOR REFERENCE)
SCK CYCLE #
is a timing diagram of an 8-bit, MSB-first SPI transfer in which CPHA
Figure 10-3 CPHA = 0 SPI Transfer Format
MSB
MULTICHANNEL COMMUNICATION INTERFACE
Freescale Semiconductor, Inc.
MSB
1
For More Information On This Product,
2
6
6
Go to: www.freescale.com
3
5
5
4
4
4
5
3
3
6
2
2
7
1
1
LSB
LSB
8
CPHA = 0 SPI TRANSFER
10-9