MC68HC16Z1CPV25 Freescale Semiconductor, MC68HC16Z1CPV25 Datasheet - Page 307

• Manufacturer Part Number: MC68HC16Z1CPV25
• Description: IC MPU 1K RAM 25MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CPV25

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: Q1141110

M68HC16 Z SERIES
USER’S MANUAL
2A, 3A ECLK Pulse Width
2B, 3B External Clock Input High/Low Time
4A, 5A Rise and Fall Time (All Outputs except CLKOUT)
4B, 5B External Clock Input Rise and Fall Time
Num
2, 3
4, 5
14A
14B
27A
29A
F1
1A
1B
9A
11
12
13
14
15
16
17
18
20
21
22
23
24
25
26
27
28
29
1
6
7
8
9
Frequency of Operation
Clock Period
ECLK Period
External Clock Input Period
Clock Pulse Width
CLKOUT Rise and Fall Time
Clock High to ADDR, FC, SIZE Valid
Clock High to ADDR, Data, FC, SIZE, High Impedance
Clock High to ADDR, FC, SIZE, Invalid
Clock Low to AS, DS, CS Asserted
AS to DS or CS Asserted (Read)
ADDR, FC, SIZE Valid to AS, CS, (and DS Read) Asserted
Clock Low to AS, DS, CS Negated
AS, DS, CS Negated to ADDR, FC SIZE Invalid (Address Hold)
AS, CS (and DS Read) Width Asserted
DS, CS Width Asserted (Write)
AS, CS (and DS Read) Width Asserted (Fast Cycle)
AS, DS, CS Width Negated
Clock High to AS, DS, R/W High Impedance
AS, DS, CS Negated to R/W High
Clock High to R/W High
Clock High to R/W Low
R/W High to AS, CS Asserted
R/W Low to DS, CS Asserted (Write)
Clock High to Data Out Valid
Data Out Valid to Negating Edge of AS, CS (Fast Write Cycle)
DS, CS Negated to Data Out Invalid (Data Out Hold)
Data Out Valid to DS, CS Asserted (Write)
Data In Valid to Clock Low (Data Setup)
Late BERR, HALT Asserted to Clock Low (Setup Time)
AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated
DS, CS Negated to Data In Invalid (Data In Hold)
DS, CS Negated to Data In High Impedance
(V
DD
3
and V
Freescale Semiconductor, Inc.
For More Information On This Product,
Table A-17 20.97-MHz AC Timing
Characteristic
DDSYN
2
6
ELECTRICAL CHARACTERISTICS
= 5.0 Vdc
Go to: www.freescale.com
5
4
2
4
3
4
7, 8
5%, V
7
SS
= 0 Vdc, T
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DVASN
t
CHAZx
CHAZn
t
t
SWAW
SWDW
SNDOI
BELCL
t
t
t
t
t
t
t
t
SNRN
CHRH
CHDO
SNDN
A
XCHL
t
CHAV
AVSA
CLSN
CHSZ
CHRL
RAAA
RASA
DVSA
CLSA
STSA
t
ECW
SNAI
SWA
DICL
SNDI
SHDI
t
Ecyc
Xcyc
t
XCrf
t
CW
cyc
Crf
t
SN
f
rf
= T
L
to T
47.7
47.7
18.8
23.8
H
Min
381
183
-10
10
10
80
36
32
32
10
10
54
10
10
10
15
—
—
—
—
—
—
—
0
0
0
0
2
0
0
5
0
0
)
1
20.97
Max
23
47
23
10
23
47
23
23
23
60
48
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
8
5
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
A-23