M30263F6AFP#U3 Renesas Electronics America, M30263F6AFP#U3 Datasheet - Page 152
![MCU 3/5V 48K I TEMP PB-FREE 42-S](/photos/28/61/286144/42-ssop_sml.jpg)
M30263F6AFP#U3
Manufacturer Part Number
M30263F6AFP#U3
Description
MCU 3/5V 48K I TEMP PB-FREE 42-S
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheet
1.M30260F3AGPU5A.pdf
(354 pages)
Specifications of M30263F6AFP#U3
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, Voltage Detect, WDT
Number Of I /o
33
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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e
E
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1
J
Figure 13.1.1. Block diagram of UARTi (i = 0 to 2)
0
6
2
9
C
0 .
B
2 /
(UART1)
0
(UART0)
(UART2)
0
2
6
CTS
CTS
i = 0 to 2
n
SMD2 to SMD0, CKDIR: Bits in the UiMR
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in the UiC0 register
CLKMD0, CLKMD1, RCSP: Bits in the UCON register
0
A
F
CTS
CTS
i
: Values set to the UiBRG register
2
e
Clock source selection
0 -
G
1
0
b
/ CLKS
0
/ RTS
2
1 .
2
o r
f
1SIO or
f
f
/ RTS
/ RTS
1SIO or
1SIO or
0
, 5
RxD
CLK
RxD
RxD
u
CLK
CLK
0
Clock source selection
p
2
f
1
Clock source selection
32SIO
f
f
f
f
2SIO
8SIO
1
32SIO
1
1
32SIO
0
f
/
f
f
f
(
8SIO
8SIO
0
2SIO
0
0
2
2SIO
2
2
0
M
CTS
7
1
01
6
0
CTS/RTS selected
CLK1 to CLK0
reversing
01
01
CKPOL
CTS/RTS
selected
00
polarity
CLK1 to CLK0
CKPOL
from UART1
2
10
CLK1 to CLK0
CKPOL
reversing
reversing
circuit
C
00
00
10
polarity
CLK
Clock output
pin select
10
polarity
page 133
2
2
circuit
CLKMD1=1
CLKMD1=0
circuit
2
CLK
2
External
CLK
External
2
2
2
2
2 /
External
Internal
Internal
6
Internal
CRS=1
CRS=1
CRS=0
reversing circuit
CRS=0
, A
RxD polarity
CKDIR=0
CKDIR=1
M
CKDIR=0
CKDIR=1
CKDIR=0
CKDIR=1
Main clock, PLL clock,
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when internal clock is selected)
or on-chip oscillator clock
1
CTS/RTS selected
f o
RCSP=0
RCSP=1
CLKMD0=0
CLKMD0=1
CTS/RTS disabled
V
6
CTS/RTS disabled
CC
3
C
1 / (n
CTS/RTS disabled
CRD=1
CRD=0
2
1 / (n
1 / (n
2 /
9
U1BRG
register
U2BRG
register
U0BRG
register
CRS=1
CRS=0
6
1
, B
Clock synchronous type
(when internal clock is selected)
0
2
+1)
s
+1)
+1)
Clock synchronous type
(when external clock is selected)
Clock synchronous type
(when external clock is selected)
Clock synchronous type
(when external clock is selected)
V
V
M
V
CC
CC
CTS/RTS disabled
CC
1
CTS/RTS disabled
CRD=1
CRD=1
CRD=0
CRD=0
CTS/RTS disabled
CRD=1
CRD=0
1/16
1/16
1/2
6
1/16
1/16
1/16
1/16
1/2
1/2
C
RTS
CTS
UART transmission
Clock synchronous type
(when internal clock is selected)
Clock synchronous
type
Clock synchronous
type
Clock synchronous
type
2 /
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when internal clock is selected)
UART transmission
Clock synchronous
type
UART reception
Clock synchronous
type
UART transmission
Clock synchronous
type
UART reception
6
UART reception
2
2
) T
1/8
RCSP=1
1/2
RCSP=0
RTS
CTS
SMD2 to SMD0
SMD2 to SMD0
f
SMD2 to SMD0
f
2SIO
1SIO
CKDIR=1
0
CKDIR=0
0
CKDIR=1
CKDIR=0
CKDIR=1
CKDIR=0
RTS1
CTS
CTS1
1/4
Transmission control
PCLK1=0
PCLK1=1
0
Transmission
control circuit
control circuit
from UART0
control circuit
Transmission
control circuit
control circuit
Reception
Reception
Reception
circuit
f
f
f
8SIO
32SIO
1SIO or
Receive
clock
Transmit
clock
Receive
clock
Transmit
clock
Receive
clock
Transmit
clock
f
2SIO
Transmit/
Transmit/
receive
receive
Transmit/
unit
receive
unit
unit
reversing
polarity
circuit
TxD
13. Serial I/O
TxD
TxD
TxD
1
0
2
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