M30263F6AFP#U3 Renesas Electronics America, M30263F6AFP#U3 Datasheet - Page 157
![MCU 3/5V 48K I TEMP PB-FREE 42-S](/photos/28/61/286144/42-ssop_sml.jpg)
M30263F6AFP#U3
Manufacturer Part Number
M30263F6AFP#U3
Description
MCU 3/5V 48K I TEMP PB-FREE 42-S
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheet
1.M30260F3AGPU5A.pdf
(354 pages)
Specifications of M30263F6AFP#U3
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, Voltage Detect, WDT
Number Of I /o
33
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R
R
M
e
E
. v
1
J
6
Figure 13.1.6. U0C0 to U2C0 registers and UCON register
0
2
9
C
0 .
B
2 /
0
0
2
6
0
A
F
2
e
NOTES:
0 -
G
b
UART Transmit/receive Control Register 2
1 .
b7
1. Set the corresponding port direction bit for each CTSi pin to “0” (input mode).
2. Effective when the SMD2 to SMD0 bits in the UMR register to "001
3. CTS
4. SDA2 and SCL2 are effective when i = 2.
5. When the SMD2 to SMD0 bits in UiMR regiser are set to “000
6. When the U1MAP bit in PACR register is “1” (P7
7. When the CLK1 and CLK0 bit settings are changed, set the UiBRG register.
2
o r
NOTES:
UARTi Transmit/receive Control Rregister 0 (i=0 to 2)
b7
0
, 5
transfer data 8 bits long). Set the UFORM bit to "1" when the SMD2 to SMD0 bits are set to "101
they are set to"100
UCON register is set to “0” (CTS
SCL2 pins are N-channel open-drain output).
u
b6
0
1. To use more than one transfer clock output pins, set the CKDIR bit in the U1MR register to “0” (internal clock).
2. When the U1MAP bit in PACR register is set to “1” (P7
b6
p
2
1
b5
0
(
/RTS
b5
M
0
7
b4
b4
1
1
6
can be used when the CLKMD1 bit in the UCON register is set to “0” (only CLK
b3
b3
C
page 138
2 /
b2
b2
6
2
" (UART mode transfer data 7 bits long) or "110
b1
b1
, A
b0
b0
M
UFORM Transfer format select bit
Symbol
CKPOL
TXEPT
f o
1
CRS
CLK0
CLK1
Bit Symbol
CRD
NCH
CLKMD0
CLKMD1
Bit
6
U0RRM
U1RRM
U0IRS
U1IRS
RCSP
3
C
0
(b7)
2
Symbol
U0C0 to U2C0
/RTS
2 /
9
Symbol
UCON
(2)
6
BRG count source
select bit
CTS/RTS function
select bit
Transmit register empty
flag
CTS/RTS disable bit
Data output select bit
CLK polarity select bit
0
, B
not separated).
UART0 transmit interrupt
cause select bit
UART1 transmit interrupt
cause select bit
UART0 continuous
receive mode enable bit
UART1 continuous
receive mode enable bit
UART1 CLK/CLKS
select bit 0
UART1 CLK/CLKS
select bit 1
Separate UART0
CTS/RTS bit
Nothing is assigned. When write, set to “0”.
When read, the content is indeterminate
M
Bit Name
1
(3)
(7)
3
6
to P7
C
Bit Name
Address
03A4
2 /
0
(1)
Address
03B0
), CTS/RTS pin in UART1 is assigned to P7
6
16
) T
, 03AC
(5)
2
16
” (serial I/O disable), do not set NCH bit to “1” (TxDi/SDA2 and
3
0 0 : f
0 1 : f
1 0 : f
1 1 : Do not set
Effective when CRD is set to "0"
0 : CTS function is selected
1 : RTS function is selected
0 : Data in transmit register (during transmission)
1 : No data in transmit register
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
0 : TxDi/SDA2 and SCL2 pins are CMOS output
1 : TxDi/SDA2 and SCL2 pins are N-channel open-drain output
0 : LSB first
1 : MSB first
b1 b0
0 : Transmit data is output at falling edge of transfer clock
1 : Transmit data is output at rising edge of transfer clock
to P7
16
2
(P6
(transmission completed)
and receive data is input at rising edge
and receive data is input at falling edge
"(clock synchronous serial I/O mode) or "010
2
, 037C
" ( UART mode transfer data 9 bits long).
1SIO
8SIO
32SIO
0
0
), CTS
, P6
0: Transmit buffer empty (Tl = 1)
1: Transmission completed (TXEPT = 1)
0: Transmit buffer empty (Tl = 1)
1: Transmission completed (TXEPT = 1)
0: Continuous receive mode disabled
1: Continuous receive mode enable
0: Continuous receive mode disabled
1: Continuous receive mode enabled
Effective when CLKMD1 bit is set to “1”
0: Clock output from CLK1
1: Clock output from CLKS1
0: Output from CLK1 only
1: Transfer clock output from multiple
0: CTS/RTS shared pin
1: CTS/RTS separated (CTS
or f
is selected
16
is selected
4
pins function selected
from the P6
and P7
2SIO
0
After Reset
X0000000
is supplied from the P7
After Reset
00001000
is selected
3
can be used as I/O ports)
4
pin)
2
2
1
Function
(1)
Function
output) and the RCSP bit in the
(2)
2
" (I
0
2
.
C bus mode) and "0" when
0
0
supplied
pin.
(6)
2
" (UART mode
RW
RW
RW
RW
RW
RW
RW
RW
(4)
RW
RW
RW
RW
RW
RW
RO
RW
RW
13. Serial I/O
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