M30263F6AFP#U3 Renesas Electronics America, M30263F6AFP#U3 Datasheet - Page 173
![MCU 3/5V 48K I TEMP PB-FREE 42-S](/photos/28/61/286144/42-ssop_sml.jpg)
M30263F6AFP#U3
Manufacturer Part Number
M30263F6AFP#U3
Description
MCU 3/5V 48K I TEMP PB-FREE 42-S
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheet
1.M30260F3AGPU5A.pdf
(354 pages)
Specifications of M30263F6AFP#U3
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, Voltage Detect, WDT
Number Of I /o
33
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R
M
e
E
. v
1
J
Figure 13.1.2.2. Receive Operation
Table 13.1.2.1.1 Example of Bit Rates and Settings
6
0
2
9
C
Bit Rate
0 .
B
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
2 /
(bps)
14400
19200
28800
31250
38400
51200
0
0
13.1.2.1. Bit Rates
1200
2400
4800
9600
2
6
0
In UART mode, the frequency set by the UiBRG register (i=0 to 2) divided by 16 become the bit rates.
Table 13.1.2.1.1 lists example of bit rate and settings.
A
F
2
UiBRG count
source
UiC1 register
RE bit
RxDi
Transfer clock
RTSi
SiRIC register
IR bit
e
UiC1 register
RI bit
The above timing diagram applies to the case where the register bits are set as follows:
i = 0 to 2
0 -
G
b
• Set the PRYE bit in the UiMR register to "0"(parity disabled)
• Set the STPS bit in the UiMR register to "0" (1 stop bit)
• Set the CRD bit in the UiC0 register to "0" (CTSi/RTSi enabled), the CRS bit to "1" (RTSi selected)
1 .
2
o r
0
, 5
u
0
Count Source
p
2
0
(
of BRG
M
0
7
1
6
f1
C
f8
f8
f8
f1
f1
f1
f1
f1
f1
page 154
“1”
“0”
“1”
“0”
“H”
“L”
“1”
“0”
2 /
6
Reception triggered when transfer clock
is generated by falling edge of start bit
, A
M
f o
1
Peripheral Function Clock : 16MHz
Set Value of BRG : n Actual Time (bps) Set Value of BRG : n Actual Time (bps)
6
3
C
Start bit
103(67h)
103(67h)
2
2 /
31(1Fh)
51(33h)
25(19h)
68(44h)
51(33h)
34(22h)
25(19h)
19(13h)
9
6
, B
Sampled “L”
Cleared to “0” when interrupt request is accepted, or cleared to “0” by program
M
1
6
C
2 /
6
) T
D
0
Receive data taken in
14493
19231
28571
31250
38462
50000
1202
2404
4808
9615
Transferred from UARTi receive
register to UiRB register
D
1
D
Peripheral Function Clock : 20MHz
7
129(81h)
129(81h)
42(2Ah)
64(40h)
32(20h)
86(56h)
64(40h)
39(27h)
32(20h)
24(18h)
Stop bit
Read out from
UiRB register
14368
19231
29070
31250
37879
50000
1202
2404
4735
9615
13. Serial I/O
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