M30263F6AFP#U3 Renesas Electronics America, M30263F6AFP#U3 Datasheet - Page 155
![MCU 3/5V 48K I TEMP PB-FREE 42-S](/photos/28/61/286144/42-ssop_sml.jpg)
M30263F6AFP#U3
Manufacturer Part Number
M30263F6AFP#U3
Description
MCU 3/5V 48K I TEMP PB-FREE 42-S
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheet
1.M30260F3AGPU5A.pdf
(354 pages)
Specifications of M30263F6AFP#U3
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, Voltage Detect, WDT
Number Of I /o
33
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R
R
M
e
E
. v
1
J
Figure 13.1.4. U0TB to U2TB registers, U0RB to U2RB registers, U0BRG to U2BRG registers
6
0
2
9
C
0 .
B
2 /
0
0
2
6
(b15)
NOTES:
NOTES:
b7
NOTES:
UARTi Receive Buffer Register (i=0 to 2)
0
UARTi Transmit Buffer Register (i=0 to 2)
b7
(b15)
b7
UARTi Baud Rate Generation Register (i=0 to 2)
A
F
1. When the SMD2 to SMD0 bits in the UiMR register are set to “000
2. The ABT bit is set to “0” by setting to “0” by program. (Writing “1” has no effect.)
2
1. Write to this register while serial I/O is neither transmitting nor receiving.
2. Use MOV instruction to write to this register.
3. Set the UiBRG register after setting the CLK1 and CLK0 bits in the UiC0 registers.
e
1. Use MOV instruction to write to this register.
0 -
G
disabled), all of the SUM, PER, FER and OER bits are set to “0” (no error). The SUM bit is set to “0” (no error) when all of the PER, FER and OER
bits are set to “0” (no error). Also, the PER and FER bits are set to “0” by reading the lower byte of the UiRB register.
Nothing is assigned at the bit 11 in the U0RB and U1RB registers. When write, set to "0". When read, its content is "0".
b
The transfer clock is shown below when the setting value in the UiBRG register is set as n.
1 .
2
o r
(1) When the CKDIR bit in the UiMR register to “0” (internal clock)
(2) When the CKDIR bit in the UiMR register to “1” (external clock)
0
, 5
u
0
p
2
0
(
M
0
• Clock synchronous serial I/O mode
• Clock asynchronous serial I/O (UART) mode
• Clock synchronous serial I/O mode
• Clock asynchronous serial I/O (UART) mode
7
1
6
C
page 136
(b8)
(b8)
b0
b0
b0
2 /
b7
b7
6
, A
M
f o
1
6
3
C
2
2 /
9
6
(b10-b9)
Symbol
(b7-b0)
Assuming that set value = n, UiBRG divides the count source
by n + 1
, B
Transmit data
Nothing is assigned.
When write, set to "0". When read, its content is indeterminate.
OER
FER
PER
SUM
ABT
(b8)
Bit
b0
b0
(1)
M
1
Arbitration lost detecting
flag
Overrun error flag
Framing error flag
Parity error flag
Error sum flag
Nothing is assigned.
When write, set to "0". When read, its content is indeterminate.
6
Symbol
U0TB
U1TB
U2TB
Symbol
U0RB
U1RB
U2RB
Symbol
U0BRG
U1BRG
U2BRG
C
(2)
(1, 2, 3)
2 /
: fj/(2(n+1))
: fj/(16(n+1))
: f
: f
EXT
EXT
6
Bit Name
2
) T
/(16(n+1))
” (serial I/O disabled) or the RE bit in the UiC1 register is set to “0” (reception
(1)
Address
03A7
03AF
037F
fj : f1SIO, f2SIO, f8SIO, f32SIO
f
Address
03A3
03AB
037B
(1)
EXT
(1)
Function
(1)
Address
03A1
03A9
0379
: Input from CLKi pin
16
16
16
16
16
16
-037E
-03A2
-037A
-03A6
-03AE
-03AA
16
16
16
0 : Not detected
1 : Detected
0 : No overrun error
1 : Overrun error found
Receive data (D
Receive data (D
0 : No framing error
1 : Framing error found
0 : No parity error
1 : Parity error found
0 : No error
1 : Error found
16
16
16
16
16
16
Function
After Reset
Indeterminate
Indeterminate
Indeterminate
After Reset
Indeterminate
Indeterminate
Indeterminate
After Reset
Indeterminate
Indeterminate
Indeterminate
7
8
)
to D
0
)
Function
Setting Range
00
16
to FF
16
13. Serial I/O
RW
RW
RW
RO
RO
RO
RO
WO
RO
RO
RW
WO
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