M30263F6AFP#U3 Renesas Electronics America, M30263F6AFP#U3 Datasheet - Page 165
![MCU 3/5V 48K I TEMP PB-FREE 42-S](/photos/28/61/286144/42-ssop_sml.jpg)
M30263F6AFP#U3
Manufacturer Part Number
M30263F6AFP#U3
Description
MCU 3/5V 48K I TEMP PB-FREE 42-S
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheet
1.M30260F3AGPU5A.pdf
(354 pages)
Specifications of M30263F6AFP#U3
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, Voltage Detect, WDT
Number Of I /o
33
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Figure 13.1.1.2.1. Polarity of transfer clock
6
0
2
9
C
0 .
B
2 /
0
0
13.1.1.1 Counter Measure for Communication Error Occurs
13.1.1.2 CLK Polarity Select Function
2
6
0
If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode,
follow the procedures below.
•Resetting the UiRB register (i=0 to 2)
•Resetting the UiTB register (i=0 to 2)
register.
Use the CKPOL bit in the UiC0 register (i = 0 to 2) to select the transfer clock polarity. Figure 13.1.1.2.1
shows the polarity of the transfer clock.
A
F
NOTES:
2
(3) “1” is written to RE bit in the UiC1 register (reception enabled), regardless to the TE bit in the UiC1
i = 0 to 2
(1) Set the RE bit in the UiC1 register to “0” (reception disabled)
(2) Set the SMD2 to SMD0 bits in the UiMR register to “000
(3) Set the SMD2 to SMD0 bits in the UiMR register to “001
(4) Set the RE bit in the UiC1 register to “1” (reception enabled)
(1) Set the SMD2 to SMD0 bits in the UiMR register to “000
(2) Set the SMD2 to SMD0 bits in the UiMR register to “001
e
R
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(1) When the CKPOL bit in the UiC0 register is set to "0" (transmit data output at the falling
CLK
T
CLK
T
(2) When the CKPOL bit in the UiC0 register is set to "1" (transmit data output at the rising
0 -
G
b
X
X
X
X
1 .
D
D
1. This applies to the case where the UFORM bit in the UiC0 register is set to "0" (LSB first) and the
2. When not transferring, the CLKi pin outputs a high signal.
3. When not transferring, the CLKi pin outputs a low signal.
D
D
2
o r
edge and the receive data taken in at the rising edge of the transfer clock)
edge and the receive data taken in at the falling edge of the transfer clock)
0
i
i
i
i
i
i
, 5
u
UiLCH bit in the UiC1 register is set to "0" (no reverse).
0
p
2
0
(
M
0
7
1
6
C
page 146
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6
D0
D
D
D
, A
0
0
0
M
f o
1
D
D
D
D
6
1
1
3
1
1
C
2
2 /
9
6
D
D
, B
D
D
2
2
2
2
M
1
6
D
D
D
D
C
3
3
3
3
2 /
6
) T
D
D
D
D
4
4
4
4
D
D
D
D
5
5
5
5
D
D
D
D
6
6
6
6
2
2
2
2
” (Serial I/O disabled)
” (Clock synchronous serial I/O mode)
” (Serial I/O disabled)
” (Clock synchronous serial I/O mode)
D
D
D
D
7
7
7
7
(2)
(3)
13. Serial I/O
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