M30263F6AFP#U3 Renesas Electronics America, M30263F6AFP#U3 Datasheet - Page 92
![MCU 3/5V 48K I TEMP PB-FREE 42-S](/photos/28/61/286144/42-ssop_sml.jpg)
M30263F6AFP#U3
Manufacturer Part Number
M30263F6AFP#U3
Description
MCU 3/5V 48K I TEMP PB-FREE 42-S
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheet
1.M30260F3AGPU5A.pdf
(354 pages)
Specifications of M30263F6AFP#U3
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, Voltage Detect, WDT
Number Of I /o
33
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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e
E
1
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J
Figure 9.4.3.2. Operation of Saving Register
6
0
2
C
9
0 .
B
2 /
The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP
at the time of acceptance of an interrupt request, is even or odd. If the stack pointer
register and the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits at a time.
Figure 9.4.3.2 shows the operation of the saving registers.
NOTE:
0
0
6
2
1. When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated
A
0
F
2
e
G
by the U flag. Otherwise, it is the ISP.
0 -
b
1 .
o r
2
0
, 5
u
0
p
2
0
(
M
0
NOTE:
7
1
(1) SP contains even number
[SP] – 5 (Odd)
[SP] – 4 (Even)
[SP] – 3 (Odd)
[SP] – 2 (Even)
[SP] – 1 (Odd)
[SP]
(2) SP contains odd number
[SP] – 5 (Even)
[SP] – 4 (Odd)
[SP] – 3 (Even)
[SP] – 2 (Odd)
[SP] – 1 (Even)
[SP]
6
1. [SP] denotes the initial value of the SP when interrupt request is acknowledged.
C
page 73
2 /
After registers are saved, the SP content is [SP] minus 4.
Address
Address
6
(Odd)
(Even)
, A
M
1
f o
6
C
3
2
2 /
9
FLG
6
FLG
, B
Stack
Stack
H
H
M
1
FLG
FLG
PC
PC
PC
PC
6
C
M
M
L
L
L
L
2 /
6
PC
PC
) T
H
H
Sequence in which order
registers are saved
Sequence in which order
registers are saved
Finished saving registers
in two operations.
(3)
(4)
(1)
(2)
(2) Saved simultaneously,
(1) Saved simultaneously,
Finished saving registers
in four operations.
all 16 bits
all 16 bits
Saved, 8 bits at a time
(1)
is even, the FLG
9. Interrupt
(1)
,
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