M30263F6AFP#U3 Renesas Electronics America, M30263F6AFP#U3 Datasheet - Page 167

• Manufacturer Part Number: M30263F6AFP#U3
• Description: MCU 3/5V 48K I TEMP PB-FREE 42-S
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30263F6AFP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 33
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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R
M
e
E
. v
1
J
Figure 13.1.1.4.1. Serial data logic switch timing
Figure 13.1.1.6.1 Transfer Clock Output From Multiple Pins
6
0
2
9
C
0 .
B
NOTES:
2 /
0
0
13.1.1.5 Serial data logic switch function (UART2)
13.1.1.6 Transfer clock output from multiple pins function (UART1)
Microcomputer
2
6
1. This applies to the case where the CKDIR bit in the U1MRregister is set to "0" (internal clock) and
2. This applies to the case where U1MAP bit in PACR register is set to “0” (P6
0
When the U2LCH bit in the U2C1 register is set to "1" (reverse), the data written to the U2TB register
has its logic reversed before being transmitted. Similarly, the received data has its logic reversed
when read from the U2RB register. Figure 13.1.1.4.1 shows serial data logic.
The CLKMD1 to CLKMD0 bits in the UCON register can choose one from two transfer clock output
pins. (See Figure 13.1.1.6.1) This function is valid when the internal clock is selected for UART1.
A
F
2
e
CLKS
the CLKMD1 bit in the UCON register is set to "1" (transfer clock output from multiple pins).
0 -
G
b
Transfer clock
Transfer clock
CLK
T
1 .
(2) When the U2LCH bit in the U2C1 register is set to "1" (reverse)
(1) When the U2LCH bit in the U2C1 register is set to "0" (no reverse)
2
o r
NOTE:
X
0
D
, 5
(no reverse)
u
0
1
1
1
p
(reverse)
1. This applies to the case where the CKPOL bit in the U2C0 register is set to "0"
2
(P6
(P6
(P6
0
(
TxD
(transmit data output at the falling edge and the receive data taken in at the rising
edge of the transfer clock) and the UFORM bit is set to "0" (LSB first).
M
TxD
0
7
7
4
5
1
)
)
)
6
2
2
C
page 148
“H”
“H”
“H”
“H”
“L”
“L”
“L”
“L”
2 /
6
, A
M
f o
1
D0
D0
6
Transfer enabled
when the CLKMD0
bit in the UCON
register is set to "0"
3
C
2
2 /
9
6
D1
D1
IN
CLK
, B
M
D2
D2
1
6
C
2 /
D3
D3
6
) T
D4
D4
Transfer enabled
when the CLKMD0
bit in the UCON
register is set to "1"
D5
D5
IN
CLK
D6
D6
D7
D7
7
to P6
4
).
13. Serial I/O