M30263F6AFP#U3 Renesas Electronics America, M30263F6AFP#U3 Datasheet - Page 166
![MCU 3/5V 48K I TEMP PB-FREE 42-S](/photos/28/61/286144/42-ssop_sml.jpg)
M30263F6AFP#U3
Manufacturer Part Number
M30263F6AFP#U3
Description
MCU 3/5V 48K I TEMP PB-FREE 42-S
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheet
1.M30260F3AGPU5A.pdf
(354 pages)
Specifications of M30263F6AFP#U3
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, Voltage Detect, WDT
Number Of I /o
33
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R
M
e
E
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1
J
Figure 13.1.1.3.1 Transfer format
0
6
2
9
C
0 .
B
2 /
0
0
13.1.1.3 LSB First/MSB First Select Function
13.1.1.4 Continuous receive mode
2
6
0
Use the UFORM bit in the UiC0 register (i = 0 to 2) to select the transfer format. Figure 13.1.1.3.1
shows the transfer format.
When the UiRRM bit (i = 0 to 2) is set to "1" (continuous receive mode), the TI bit in the UiC1 register
is set to “0” (data present in the UiTB register) by reading the UiRB register. In this case, i.e., UiRRM
bit is set to "1", do not write dummy data to the UiTB register in a program. The U0RRM and U1RRM
bits are the bit 2 and bit 3 in the UCON register, respectively, and the U2RRM bit is the bit 5 in the
U2C1 register.
A
F
2
e
0 -
G
b
1 .
2
o r
(1) When the UFORM bit in the UiC0 register "0" (LSB first)
(2) When the UFORM bit in the UiC0 register is set to "1" (MSB first)
0
, 5
R
R
CLK
T
CLK
T
NOTE:
i = 0 to 2
u
0
X
X
X
X
p
2
D
D
D
D
1. This applies to the case where the CKPOL bit in the UiC0 register is set to "0" (transmit
0
(
i
i
i
i
i
i
0
M
data output at the falling edge and the receive data taken in at the rising edge of the
transfer clock) and the UiLCH bit in the UiC1 register "0" (no reverse).
7
1
6
C
page 147
2 /
6
, A
D0
D
D
D
M
0
7
7
1
f o
6
3
C
D
D
2
D
D
2 /
9
1
1
6
6
6
, B
D
D
D
D
M
2
5
2
5
1
6
C
D
D
D
D
2 /
3
4
3
4
6
) T
D
D
D
D
4
4
3
3
D
D
D
D
5
5
2
2
D
D
D
D
6
6
1
1
D
D
D
D
7
7
0
0
13. Serial I/O
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