MCF5216CVF66 Freescale Semiconductor, MCF5216CVF66 Datasheet - Page 108

• Manufacturer Part Number: MCF5216CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5216CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Operating Temperature Range: -40°C To +85°C
• No. Of Pins: 256
• Rohs Compliant: No
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Cache
For instruction fetches, the fill buffer can also be used as temporary storage for line-sized bursts of
non-cacheable references under control of CACR[CEIB]. With this bit set, a non-cacheable instruction
fetch is processed, as defined by
references can hit in the buffer, but the data is never loaded into the memory array.
Table 4-7
4-10
shows the relationship between CACR bits CENB and CEIB and the type of instruction fetch.
[CENB]
CACR
0
0
1
1
1
[CEIB]
CACR
Table 4-7. Instruction Cache Operation as Defined by CACR
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
X
0
1
0
1
Instruction Fetch
Non-cacheable
Non-cacheable
Table
Cacheable
Type of
N/A
N/A
4-7. For this condition, the line-fill buffer is loaded and subsequent
Cache is completely disabled; all instruction fetches
are word or longword in size.
All instruction fetches are word or longword in size
Fetch size is defined by
line-fill buffer can be written into the memory array
All instruction fetches are word or longword in size,
and not loaded into the line-fill buffer
Instruction fetch size is defined by
loaded into the line-fill buffer, but are never written into
the memory array.
Description
Table 4-6
and contents of the
Table 4-6
Freescale Semiconductor
and