MCF5216CVF66 Freescale Semiconductor, MCF5216CVF66 Datasheet - Page 214

• Manufacturer Part Number: MCF5216CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5216CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Operating Temperature Range: -40°C To +85°C
• No. Of Pins: 256
• Rohs Compliant: No
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Edge Port Module (EPORT)
11.4.2.5 Edge Port Pin Data Register (EPPDR)
11.4.2.6 Edge Port Flag Register (EPFR)
11-6
Bit(s)
Bit(s)
7–1
7–1
0
0
Address
Address
Reset
Reset
EPPDx
Field
Field
Name
Name
R/W
R/W
EPFx
—
—
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
EPPD7
EPF7
Figure 11-6. EPORT Port Pin Data Register (EPPDR)
7
7
Figure 11-7. EPORT Port Flag Register (EPFR)
Edge port pin data bits. The read-only EPPDR reflects the current state of the EPORT
pins IRQ7–IRQ1. Writing to EPPDR has no effect, and the write cycle terminates
normally. Reset does not affect EPPDR.
Reserved, should be cleared.
Edge port flag bits. When an EPORT pin is configured for edge triggering, its
corresponding read/write bit in EPFR indicates that the selected edge has been
detected. Reset clears EPF7-EPF1.
Bits in this register are set when the selected edge is detected on the corresponding
pin. A bit remains set until cleared by writing a 1 to it. Writing 0 has no effect. If a pin
is configured as level-sensitive (EPPARx = 00), pin transitions do not affect this
register.
1 Selected edge for IRQx pin has been detected.
0 Selected edge for IRQx pin has not been detected.
Reserved, should be cleared.
Table 11-7. EPPDR Field Descriptions
EPPD6
Table 11-8. EPFR Field Descriptions
EPF6
6
6
EPPD5
EPF5
5
5
Current pin state
IPSBAR + 0x0013_0005
IPSBAR + 0x0013_0006
R/W
0000_0000
EPPD4
EPF4
4
4
R
Description
Description
EPPD3 EPPD2 EPPD1
EPF3
3
3
EPF2
2
2
EPF1
1
1
Freescale Semiconductor
—
—
R
0
0
0