MCF5216CVF66 Freescale Semiconductor, MCF5216CVF66 Datasheet - Page 366

• Manufacturer Part Number: MCF5216CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5216CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Operating Temperature Range: -40°C To +85°C
• No. Of Pins: 256
• Rohs Compliant: No
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Programmable Interrupt Timers (PIT0–PIT3)
19.3
This section describes the PIT functional operation.
19.3.1
This mode of operation is selected when the RLD bit in the PCSR register is set.
When PIT counter reaches a count of 0x0000, PIF flag is set in PCSRn. The value in the modulus register
loads into the counter, and the counter begins decrementing toward 0x0000. If the PCSRn[PIE] bit is set,
the PIF flag issues an interrupt request to the CPU.
When the PCSRn[OVW] bit is set, the counter can be directly initialized by writing to PMRn without
having to wait for the count to reach 0x0000.
19.3.2
This mode of operation is selected when the PCSRn[RLD] bit is clear. In this mode, the counter rolls over
from 0x0000 to 0xFFFF without reloading from the modulus latch and continues to decrement.
When the counter reaches a count of 0x0000, PCSRn[PIF] flag is set. If the PCSRn[PIE] bit is set, PIF flag
issues an interrupt request to the CPU.
19-6
IPSBAR
Field
Offset:
15–0
Reset
PC
PIT Clock
Modulus
Counter
W
R
0x15_0004 (PCNTR0)
0x16_0004 (PCNTR1)
0x17_0004 (PCNTR2)
0x18_0004 (PCNTR3)
PIF
Counter value. Reading this field with two 8-bit reads is not guaranteed coherent. Writing to PCNTRn has no effect,
and write cycles are terminated normally.
Functional Description
15
1
Set-and-Forget Timer Operation
Free-Running Timer Operation
14
1
13
1
0x0002
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure 19-5. Counter Reloading from the Modulus Latch
12
1
Figure 19-4. PIT Count Register (PCNTRn)
Table 19-5. PCNTRn Field Descriptions
11
1
10
1
0x0001
1
9
Description
1
8
0x0005
PC
1
7
1
6
0x0000
1
5
4
1
1
3
Freescale Semiconductor
Access: User read only
0x0005
1
2
1
1
1
0