MCF5216CVF66 Freescale Semiconductor, MCF5216CVF66 Datasheet - Page 612

• Manufacturer Part Number: MCF5216CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5216CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Operating Temperature Range: -40°C To +85°C
• No. Of Pins: 256
• Rohs Compliant: No
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Reset Controller Module
29.4.2
The RSR contains a status bit for every reset source. When reset is entered, the cause of the reset condition
is latched along with a value of 0 for the other reset sources that were not pending at the time of the reset
condition. These values are then reflected in RSR. One or more status bits may be set at the same time.
The cause of any subsequent reset is also recorded in the register, overwriting status from the previous reset
condition.
RSR can be read at any time. Writing to RSR has no effect.
29-4
Bit(s)
Bit(s)
3
2
1
0
7
6
5
4
Reset Status Register (RSR)
LVDRE
Name
LVDIE
Name
SOFT
LVDE
WDR
LVD
Address
—
—
Reset
Field
R/W
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
—
Table 29-3. RCR Field Descriptions (continued)
LVD interrupt enable. Controls the LVD interrupt if LVDE is set. This bit has no effect if
the LVDE bit is a logic 0.
1 LVD interrupt enabled
0 LVD interrupt disabled
LVD reset enable. Controls the LVD reset if LVDE is set. This bit has no effect if the
LVDE bit is a logic 0. LVD reset has priority over LVD interrupt, if both are enabled.
1 LVD reset enabled
0 LVD reset disabled
Reserved, should be cleared.
Controls whether the LVD is enabled.
1 LVD is enabled
0 LVD is disabled
Reserved, should be cleared.
Low voltage detect. Indicates that the last reset state was caused by an LVD reset.
1 Last reset state was caused by an LVD reset
0 Last reset state was not caused by an LVD reset
Software reset flag. Indicates that the last reset was caused by software.
1 Last reset caused by software
0 Last reset not caused by software
Watchdog timer reset flag. Indicates that the last reset was caused by a watchdog
timer timeout.
1 Last reset caused by watchdog timer timeout
0 Last reset not caused by watchdog timer timeout
7
Figure 29-3. Reset Status Register (RSR)
Table 29-4. RSR Field Descriptions
LVD
6
SOFT
5
IPSBAR + 0x11_0001
Reset Dependent
WDR
4
R
POR
Description
Description
3
EXT
2
LOC
1
LOL
0
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