MCF5216CVF66 Freescale Semiconductor, MCF5216CVF66 Datasheet - Page 742

• Manufacturer Part Number: MCF5216CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5216CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Operating Temperature Range: -40°C To +85°C
• No. Of Pins: 256
• Rohs Compliant: No
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Revision History
B-6
Table 17-13/17-26
Figure 33-5/33-16
Table 14-3/14-11
Figure 12-4/12-8
Table 33-1/33-1
Table 33-6/33-8
Figure 9-1/9-3
Table 8-3/8-5
10.3.6/10-11
Figure 23-11
24.6.1/24-11
Chapter 19
19.6.3/19-7
27.2.1/27-2
Chapter 33
10.5/10-17
13.5/13-15
Location
32.2/32-7
Remove ÷ 2 from CLKGEN block.
Changed CSCRn to reflect that AA is set at reset.
Removed final paragraph. The paragraph incorrectly states that the MCF5282 does not have a bus
Changed pull-up indications in the ‘Internal Pull-Up’ column.
Change encodings for bits 31–9 to:
Change UISR bits 5–3 to reserved bits
Changed ‘When interfacing to 16-bit ports, the port C and D pins and PJ[5:4] (BS[1:0]) can be configured
Add the following note to the BDE bit description: “The SPV bit in the CPU’s RAMBAR must also be set
to allow dual port access to the SRAM. For more information, see Section 5.3.1, ‘SRAM Base Address
Register (RAMBAR).’”
Add this text to the end of the first paragraph: “If a specific interrupt request is completely unused, the
ICRnx value can remain in its reset (and disabled) state.”
Added the following note: “The wakeup mask level taken from LPICR[6:4] is adjusted by hardware to allow
a level 7 IRQ to generate a wakeup. That is, the wakeup mask value used by the interrupt controller must
be in the range of 0–6.”
monitor.
Change PIT1–PIT4 to PIT0–PIT3 throughout chapter. When a timer is referenced individually, PIT1
should be PIT0, PIT2 should be PIT1, PIT3 should be PIT2, and PIT4 should be PIT3. Other chapters in
the user’s manual use the correct nomenclature: PIT0–PIT3.
Change timeout period equation to the equation below.
Change ‘I2CR = 0xA’ to ‘I2CR = 0xA0.’
as general-purpose input/output (I/O)’
Added additional device number order information to
80-MHz, and MCF5282 at 80 MHz.
Delete references to ‘T
Replace V
Replace I
to 5.0 mA.
Replaced figure, “SDRAM Read Cycle”
Timeout period
0 The corresponding interrupt source is masked.
1The corresponding interrupt source is not masked.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
DDA
in
Table B-3. Rev. 1 to Rev. 2 Changes (continued)
row with the row below, in which the maximum value has been changed to 6.0 V.
row with the row below, in which the maximum value in normal operation has been changed
=
PRE[3:0] (PM[15:0]
-----------------------------------------------------------------------------
A
= T
system clock
L
×
to T
H
’.
+
1)
×
Description
2
Table 32-2
for MCF5280 and MCF5281 at 66- and
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