MCF5216CVF66 Freescale Semiconductor, MCF5216CVF66 Datasheet - Page 166

• Manufacturer Part Number: MCF5216CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5216CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Operating Temperature Range: -40°C To +85°C
• No. Of Pins: 256
• Rohs Compliant: No
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

System Control Module (SCM)
and writes. Each PACR follows the format illustrated in
that they control, refer to
8-14
Bits
6–4 ACCESS_CTRL1 This 3-bit field defines the access control for the given platform peripheral.
2–0 ACCESS_CTRL0 This 3-bit field defines the access control for the given platform peripheral.
7
3
Address
IPSBAR Offset
Reset
Field
R/W
0x024
0x025
0x026
LOCK1
LOCK0
Name
LOCK1
7
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 8-11. Peripheral Access Control Registers (PACRs)
Figure 8-9. Peripheral Access Control Register (PACRn)
Table
This bit, when set, prevents subsequent writes to ACCESSCTRL1. Any attempted
write to the PACR generates an error termination and the contents of the register are
not affected. Only a system reset clears this flag.
The encodings for this field are shown in
This bit, when set, prevents subsequent writes to ACCESSCTRL0. Any attempted
write to the PACR generates an error termination and the contents of the register are
not affected. Only a system reset clears this flag.
The encodings for this field are shown in
Table 8-10. PACR ACCESSCTRL Bit Encodings
8-11.
Bits
000
001
010
011
100
101
110
111
6
Table 8-9. PACR Field Descriptions
ACCESS_CTRL1
PACR0
PACR1
PACR2
Name
Read/Write
Read
Read
Read
Read/Write
Read/Write
Read/Write
No Access
Supervisor Mode
IPSBAR + 0x24 + Offset
4
0000_0000
Figure
R/W
Description
ACCESS_CTRL1
No Access
No Access
Read
No Access
Read/Write
Read
Read/Write
No Access
LOCK0
UART0
Table
Table
SCM
8-9. For a list of PACRs and the modules
EIM
3
User Mode
Modules Controlled
8-10.
8-10.
2
ACCESS_CTRL0
ACCESS_CTRL0
SDRAMC
UART1
DMA
Freescale Semiconductor
0