EM351-RTR Ember, EM351-RTR Datasheet - Page 107

• Manufacturer Part Number: EM351-RTR
• Description: IC RF TXRX ZIGBEE 128KB 48QFN
• Manufacturer: Ember

Specifications of EM351-RTR

• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Power - Output: 3dBm
• Sensitivity: -100dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 26mA
• Current - Transmitting: 31mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 12kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Other names: 636-1010-2

SC1_UARTFRAC
UART Baud Rate Fractional Period Register
8.7
Bitname
SC_UARTFRAC
31
23
15
0
0
0
7
0
DMA Channels
The EM35x serial DMA channels enable efficient, high-speed operation of the SPI and UART controllers by
reducing the load on the CPU as well as decreasing the frequency of interrupts that it must service. The
transmit and receive DMA channels can transfer data between the transmit and receive FIFOs and the DMA
buffers in main memory as quickly as it can be transmitted or received. Once software defines, configures,
and activates the DMA, it only needs to handle an interrupt when a transmit buffer has been emptied or a
receive buffer has been filled. The DMA channels each support two memory buffers, labeled A and B, and can
alternate (“ping-pong”) between them automatically to allow continuous communication without critical
interrupt timing.
Note: DMA memory buffer terminology
To use a DMA channel, software should follow these steps:
30
22
14
6
0
0
0
0
load - make a buffer available for the DMA channel to use
pending – a buffer loaded but not yet active
active - the buffer that will be used for the next DMA transfer
unload – DMA channel action when it has finished with a buffer
idle – a buffer that has not been loaded, or has been unloaded
Reset the DMA channel by setting the SC_TXDMARST (or SC_RXDMARST) bit in the SCx_DMACTRL register.
Set up the DMA buffers. The two DMA buffers, A and B, are defined by writing the start address to
SCx_TXBEGA/B (or SCx_RXBEGA/B) and the (inclusive) end address to SCx_TXENDA/B (or SCx_RXENDA/B).
Note that DMA buffers must be in RAM.
Configure and initialize SCx for the desired operating mode.
Enable second-level interrupts triggered when DMA buffers unload by setting the INT_SCTXULDA/B (or
INT_SCRXULDA/B) bits in the INT_SCxFLAG register.
Enable top-level NVIC interrupts by setting the INT_SCx bit in the INT_CFGSET register.
Start the DMA by loading the DMA buffers by setting the SC_TXLODA/B (or SC_RXLODA/B) bits in the
SCx_DMACTRL register.
Bitfield
[0]
29
21
13
5
0
0
0
0
Access
RW
The fractional part of the baud rate period (F) in the equation:
rate = 24MHz / ( (2 * N) + F )
Description
28
20
12
4
0
0
0
0
Final
8-32
27
19
11
3
0
0
0
0
26
18
10
0
0
0
2
0
Address: 0x4000C86C Reset: 0x0
EM351 / EM357
25
17
0
0
9
0
1
0
120-035X-000G
SC_UARTFRAC
24
16
0
0
8
0
0