EM351-RTR Ember, EM351-RTR Datasheet - Page 141

• Manufacturer Part Number: EM351-RTR
• Description: IC RF TXRX ZIGBEE 128KB 48QFN
• Manufacturer: Ember

Specifications of EM351-RTR

• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Power - Output: 3dBm
• Sensitivity: -100dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 26mA
• Current - Transmitting: 31mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 12kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Other names: 636-1010-2

Because the buffer registers are only transferred to the shadow registers when a UEV occurs, before starting
the counter initialize all the registers by setting the TIM_UG bit in the TIMx_EGR register.
OCy polarity is software programmable using the TIM_CCyP bit in the TIMx_CCER register. It can be
programmed as active high or active low. OCy output is enabled by the TIM_CCyE bit in the TIMx_CCER
register. Refer to the TIMx_CCER register description in the Registers section for more details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRy are always compared to determine whether
TIMx_CCRy ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRy, depending on the direction of the counter. The OCyREF
signal is asserted only:
This allows software to force a PWM output to a particular state while the timer is running.
The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the TIM_CMS
bits in the TIMx_CR1 register.
9.3.9.1
Up-counting is active when the TIM_DIR bit in the TIMx_CR1 register is low. Refer to the section Up-Counting
Mode.
The following example uses PWM mode 1. The reference PWM signal OCyREF is high as long as
TIMx_CNT < TIMx_CCRy, otherwise it becomes low. If the compare value in TIMx_CCRy is greater than the
auto-reload value in TIMx_ARR, then OCyREF is held at 1. If the compare value is 0, then OCyREF is held at 0.
Figure 9-22 shows some edge-aligned PWM waveforms in an example, where TIMx_ARR = 8.
9.3.9.2
Down-counting is active when the TIM_DIR bit in the TIMx_CR1 register is high. Refer to the Down-Counting
Mode section for more information.
In PWM mode 1, the reference signal OCyREF is low as long as TIMx_CNT > TIMx_CCRy, otherwise it becomes
high. If the compare value in TIMx_CCRy is greater than the auto-reload value in TIMx_ARR, then OCyREF is
held at 1. Zero-percent PWM is not possible in this mode.
When the result of the comparison changes, or
When the output compare mode (TIM_OCyM bits in the TIMx_CCMR1 register) switches from the “frozen”
configuration (no comparison, TIM_OCyM = 000) to one of the PWM modes (TIM_OCyM = 110 or 111).
PWM Edge-Aligned Mode: Up-Counting Configuration
PWM Edge-Aligned Mode: Down-Counting Configuration
Figure 9-22. Edge-Aligned PWM Waveforms (ARR = 8)
Final
9-17
120-035X-000G