EM351-RTR Ember, EM351-RTR Datasheet - Page 49

IC RF TXRX ZIGBEE 128KB 48QFN

EM351-RTR

Manufacturer Part Number
EM351-RTR
Description
IC RF TXRX ZIGBEE 128KB 48QFN
Manufacturer
Ember
Datasheets

Specifications of EM351-RTR

Frequency
2.4GHz
Data Rate - Maximum
250kbps
Modulation Or Protocol
802.15.4 Zigbee
Power - Output
3dBm
Sensitivity
-100dBm
Voltage - Supply
2.1 V ~ 3.6 V
Current - Receiving
26mA
Current - Transmitting
31mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 12kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Applications
-
Other names
636-1010-2

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EM351-RTR
Manufacturer:
SILICONLABOR
Quantity:
4 550
6.4
6.5
System Timers
Power Management
6.4.1
The EM35x integrates a watchdog timer which can be enabled to provide protection against software crashes
and ARM
watchdog timer uses the calibrated 1 kHz clock (CLK1K) as its reference and provides a nominal 2.048 s
timeout. A low water mark interrupt occurs at 1.792 s and triggers an NMI to the ARM
early warning. When the watchdog is enabled, the timer must be periodically reset before it expires. The
watchdog timer is paused when the debugger halts the ARM
that implements deep sleep functionality disables the watchdog when entering deep sleep and restores the
watchdog, if it was enabled, when exiting deep sleep.
Ember software provides an API for enabling, resetting, and disabling the watchdog timer.
6.4.2
The EM35x integrates a 32-bit timer dedicated to system timing and waking from sleep at specific times. The
sleep timer can use either the calibrated 1 kHz reference (CLK1K), or the 32 kHz crystal clock (CLK32K). The
default clock source is the internal 1 kHz clock.
The sleep timer has a prescaler, a divider of the form 2^N, where N can be programmed from 1 to 2^15. This
divider allows for very long periods of sleep to be timed. Ember software’s default configuration is to use the
prescaler to always produce a 1024 Hz sleep timer tick. The timer provides two compare outputs and wrap
detection, all of which can be used to generate an interrupt or a wake up event.
While it is possible to do so, by default the sleep timer is not paused when the debugger halts the ARM
Cortex
To save current during deep sleep, the low-frequency internal RC oscillator (OSCRC) can be turned off. If
OSCRC is turned off during deep sleep and a low-frequency 32.768 kHz crystal oscillator is not being used,
then the sleep timer will not operate during deep sleep and sleep timer wake events cannot be used to wake
up the EM35x.
Ember software provides the system timer software API for interacting with the sleep timer as well as using
the sleep timer and RC oscillator during deep sleep.
Note: Because the system timer software module handles all interactions with the sleep timer, the module
will return the correct value in all situations. In the situation where the chip performs a deep sleep that
maintains the system time and is woken up from an external event (that is, not a sleep timer event), the deep
sleep module in the Ember software delays until the next sleep timer clock tick (up to 1 ms) to guarantee that
the sleep timer updates correctly.
6.4.3
The SysTick timer is an ARM
the FCLK (the clock going into the CPU) or the Sleep Timer clock. FCLK is either the SYSCLK or PCLK as
selected by CPU_CLKSEL register (see the Clock Switching section).
The EM35x’s power management system is designed to achieve the lowest deep sleep current consumption
possible while still providing flexible wakeup sources, timer activity, and debugger operation. The EM35x has
four main sleep modes:
Idle Sleep: Puts the CPU into an idle state where execution is suspended until any interrupt occurs. All
power domains remain fully powered and nothing is reset.
TM
®
-M3. Ember does not advise pausing the sleep timer when the debugger halts the CPU.
Watchdog Timer
Sleep Timer
Event Timer
Cortex
TM
-M3 CPU lockup. By default, it is disabled at power up of the always-on power domain. The
®
standard system timer in the NVIC. The SysTick timer can be clocked from either
Final
6-11
®
Cortex
TM
-M3. Additionally, the Ember software
EM351 / EM357
®
Cortex
TM
-M3 NVIC as an
120-035X-000G
®

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