EM351-RTR Ember, EM351-RTR Datasheet - Page 12

IC RF TXRX ZIGBEE 128KB 48QFN

EM351-RTR

Manufacturer Part Number
EM351-RTR
Description
IC RF TXRX ZIGBEE 128KB 48QFN
Manufacturer
Ember
Datasheets

Specifications of EM351-RTR

Frequency
2.4GHz
Data Rate - Maximum
250kbps
Modulation Or Protocol
802.15.4 Zigbee
Power - Output
3dBm
Sensitivity
-100dBm
Voltage - Supply
2.1 V ~ 3.6 V
Current - Receiving
26mA
Current - Transmitting
31mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 12kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Applications
-
Other names
636-1010-2

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EM351-RTR
Manufacturer:
SILICONLABOR
Quantity:
4 550
Pin # Signal
32
33
34
35
SC1MOSI
SC1SCL
SC1RXD
TIM2C2
(see also Pin 25)
TIM2C2
(see also Pin 25)
SWCLK
JTCK
PC2
JTDO
SWO
PC3
JTDI
PC4
Direction
I/O
I
O
I
I/O
I
I/O
O
O
I/O
I
I/O
I
Description
SPI slave data in of Serial Controller 1
Select SPI with SC1_MODE
Select slave with SC1_SPICR
TWI clock of Serial Controller 1
Either disable timer output in TIM2_CCER,
or disable remap with TIM2_OR[5]
Select TWI with SC1_MODE
Select alternate open-drain output function with GPIO_PBCFGL[11:8]
UART receive data of Serial Controller 1
Select UART with SC1_MODE
Timer 2 channel 2 output
Enable remap with TIM2_OR[5]
Enable timer output in TIM2_CCER
Select alternate output function with GPIO_PBCFGL[11:8]
Timer 2 channel 2 input
Enable remap with TIM2_OR[5]
Serial Wire clock input/output with debugger
Selected when in Serial Wire mode (see JTMS description, Pin 35)
JTAG clock input from debugger
Selected when in JTAG mode (default mode, see JTMS description,
Pin 35)
Internal pull-down is enabled
Digital I/O
Enable with GPIO_DBGCFG[5]
JTAG data out to debugger
Selected when in JTAG mode (default mode, see JTMS description,
Pin 35)
Serial Wire Output asynchronous trace output to debugger
Select asynchronous trace interface in ARM core
Enable trace interface in ARM core
Select alternate output function with GPIO_PCCFGL[11:8]
Enable Serial Wire mode (see JTMS description, Pin 35)
Internal pull-up is enabled
Digital I/O
Either Enable with GPIO_DBGCFG[5],
or enable Serial Wire mode (see JTMS description)
JTAG data in from debugger
Selected when in JTAG mode (default mode, see JTMS description,
Pin 35)
Internal pull-up is enabled
Digital I/O
Enable with GPIO_DBGCFG[5]
Final
1-7
EM351 / EM357
120-035X-000G

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