XR17V354IB176-F Exar Corporation, XR17V354IB176-F Datasheet - Page 13

• Manufacturer Part Number: XR17V354IB176-F
• Description: IC UART PCIE 256B DUAL 176FPBGA
• Manufacturer: Exar Corporation

Specifications of XR17V354IB176-F

• Number Of Channels: 4, QUART
• Package / Case: 176-LFBGA
• Features: *
• Fifo's: 256 Byte
• Protocol: RS485
• Voltage - Supply: 3.3V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 25 Mbps
• Supply Current: 120 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• No. Of Channels: 4
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: BGA
• No. Of Pins: 176
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REV. 1.0.1
N
The V354 provides an interface to an Electrically Erasable Programmable Read Only Memory (EEPROM). The
EEPROM must be a 93C46-like device, with its memory configured as 16-bit words. This interface is provided
in order to program the registers in the PCI Configuration Space of the PCI UART during power-up. The
EEPROM must be organized into address/data pairs. The first word of the pair is the address and the second
word is the data.
1.2
0xB4-0xFF 31:0
OTE
A
O
0x104-
0x100
0x113
0x114
DDRESS
0xB0
FFSET
: EWR=Read/Write from external EEPROM. RWR=Read/Write. RO= Read Only. RWC=Read/Write-Clear.
EEPROM Interface
31:0
31:0
31:0
31:0
B
ITS
Table 2
B
13:8
7:0
IT
15
14
(
S
)
T
RO
RO
RO
RO
RO
T
YPE
below shows the format of the 16-bit address:
ABLE
1: PCI L
T
PCIe Capability Offset 0x30 - Link Status2/Control2
Not implemented or not applicable (return zeros)
VC Resource Capability Register
Not implemented or not applicable (return zeros)
VC Offset 0x4
ABLE
Parity Bit - Odd parity over entire address/data pair
If there is a parity error, it will be reported in bit-3 of the REGB register in
the Device Configuration Registers (offset 0x08E).
Final Address
If 1, this will be the last data to be read.
If 0, there will be more data to be read after this.
Reserved - Bits must be ’0’
Target Address - See
2: EEPROM A
OCAL
B
US
C
ONFIGURATION
Table 3
DDRESS
13
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
D
ESCRIPTION
D
B
EFINITION
IT
D
S
EFINITIONS
PACE
R
EGISTERS
(
HEX OR BINARY
0x8000000FF
XR17V354
R
0x00010001
0x00000000
0x00010002
0x00000000
ESET
V
ALUE
)