XR17V354IB176-F Exar Corporation, XR17V354IB176-F Datasheet - Page 18

• Manufacturer Part Number: XR17V354IB176-F
• Description: IC UART PCIE 256B DUAL 176FPBGA
• Manufacturer: Exar Corporation

Specifications of XR17V354IB176-F

• Number Of Channels: 4, QUART
• Package / Case: 176-LFBGA
• Features: *
• Fifo's: 256 Byte
• Protocol: RS485
• Voltage - Supply: 3.3V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 25 Mbps
• Supply Current: 120 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• No. Of Channels: 4
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: BGA
• No. Of Pins: 176
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
INT0 [7:0] Channel Interrupt Indicator
Each bit gives an indication of the channel that has requested for service. Bit [0] represents channel 0 and
bit [3] indicates channel 3. The upper four bits INT0[7:4] are reserved. Logic 1 indicates the channel N [3:0] has
called for service. The interrupt bit clears after reading the appropriate register of the interrupting channel
register, see Interrupt Clearing section.
INT3, INT2 and INT1 [31:8] 3-bit Channel Interrupt Encoding
Each channel’s interrupt is encoded into 3 bits for receive, transmit, and status. Bits [10:8] represent channel 0
and go up to channel 3 with bits [19:17]. The 3-bit encoding and their priority order are shown below in
The wake-up interrupt, timer/counter interrupt and MPIO interrupt are only reported in channel 0 of INT1
(bits[10:8]). These interrupts are not reported in any other location.
F
P
IGURE
RIORITY
1
2
3
4
5
6
7
0
x
Reserved
4. T
0
B
HE
0
IT
[
0
0
0
0
1
1
1
1
N
G
+2]
INT3 Register
0
LOBAL
Reserved
0
B
IT
I
T
[
NTERRUPT
0
0
1
1
0
0
1
1
N
ABLE
0
+1]
The INT0 register provides individual status for each channel
0
7: UART C
Reserved
B
0
IT
0
1
0
1
0
1
0
1
Rsvd
R
[
N
EGISTER
0
]
0
Rsvd
None or wake-up indicator (wake-up indicator is reported in channel 0 only)
RXRDY and RX Line Status (logic OR of LSR[4:1])
RXRDY Time-out
TXRDY, THR or TSR (auto RS485 mode) empty
MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon det. or special char. detected
Reserved.
MPIO pin(s). Reported in channel 0 only.
Timer/Counter. Reported in channel 0 only.
Individual UART Channel Interrupt Status
0
0
HANNEL
Reserved
, INT0, INT1, INT2
Rsvd
0
0
INT0, INT1, INT2 and INT3
INT2 Register
Interrupt Registers,
INT0 Register
Rsvd
[3:0] I
0
0
18
N+2
Bit
Bit-3 Bit-2 Bit-1 Bit-0
Ch-3 Ch-2 Ch-1 Ch-0
NTERRUPT
Channel-3
N+1
Bit
Bit
N
AND
I
NTERRUPT
S
N+2
Bit
INT3
OURCE
Channel-2
Rsvd Rsvd Rsvd Rsvd
N+1
0
Bit
E
S
Bit
0
N
NCODING
OURCE
N+2
0
Bit
Channel-1
(
INT0 Register
S
N+1
Bit
0
INT1 Register
)
Bit-3
Ch-3 Ch-2 Ch-1 Ch-0
Bit
N
Bit-2
N+2
Bit
Channel-0
Bit-1
N+1
Bit
REV. 1.0.1
Bit-0
Bit
N
Table
7.