XR17V354IB176-F Exar Corporation, XR17V354IB176-F Datasheet - Page 43

• Manufacturer Part Number: XR17V354IB176-F
• Description: IC UART PCIE 256B DUAL 176FPBGA
• Manufacturer: Exar Corporation

Specifications of XR17V354IB176-F

• Number Of Channels: 4, QUART
• Package / Case: 176-LFBGA
• Features: *
• Fifo's: 256 Byte
• Protocol: RS485
• Voltage - Supply: 3.3V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 25 Mbps
• Supply Current: 120 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• No. Of Channels: 4
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: BGA
• No. Of Pins: 176
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REV. 1.0.1
The host may fill the transmit FIFO with up to 256 bytes of transmit data. The THR empty flag (LSR bit [5]) is
set whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit [1])
when the amount of data in the FIFO falls below its programmed trigger level (see TXTRG register). The
transmit empty interrupt is enabled by IER bit [1]. The TSR flag (LSR bit [6]) is set when TSR becomes
completely empty. Furthermore, with the RS485 half-duplex direction control enabled (FCTR bit [5]=1) the
source of the transmit empty interrupt changes to TSR empty instead of THR empty. This is to ensure the
RTS# output is not changed until the last stop bit of the last character is shifted out.
The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by FCTR
bit [5]. It de-asserts RTS# or DTR# after a specified delay indicated in MSR[7:4] following the last stop bit of the
last character that has been transmitted. This helps in turning around the transceiver to receive the remote
station’s response. The delay optimizes the time needed for the last transmission to reach the farthest station
on a long cable network before switching off the line driver. This delay prevents undesirable line signal
disturbance that causes signal degradation. It also changes the transmitter empty interrupt to TSR empty
instead of THR empty.
F
3.6.3
3.6.4
IGURE
F
IGURE
1 6 X o r 8 X o r 4 X
13. T
14. T
Transmitter Operation in FIFO Mode
Auto RS485 Operation
C lo c k
(Xoff1/2 and Xon1/2 Reg.
Auto Software Flow Control
Flow Control Characters
Auto CTS Flow Control (CTS# pin)
16X or 8X or 4X
RANSMITTER
D a t a
B y t e
RANSMITTER
Clock
O
PERATION IN NON
O
Data Byte
Transmit
T r a n s m it S h if t R e g is t e r ( T S R )
PERATION IN
T r a n s m it
R e g i s t e r
H o ld i n g
( T H R )
FIFO
-FIFO M
Transmit Data Shift Register
AND
(256-Byte)
Transmit
F
ODE
FIFO
(TSR)
LOW
43
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
C
ONTROL
M
T H R I n t e r r u p t ( I S R b i t - 1 )
ODE
E n a b le d b y I E R b it - 1
THR Interrupt (ISR bit-1) falls
when becomes empty. FIFO
below Programmed Trigger
is Enabled by FCR bit-0=1
Level (TXTRG) and then
M
S
B
XR17V354
L
S
B