XR17V354IB176-F Exar Corporation, XR17V354IB176-F Datasheet - Page 30

• Manufacturer Part Number: XR17V354IB176-F
• Description: IC UART PCIE 256B DUAL 176FPBGA
• Manufacturer: Exar Corporation

Specifications of XR17V354IB176-F

• Number Of Channels: 4, QUART
• Package / Case: 176-LFBGA
• Features: *
• Fifo's: 256 Byte
• Protocol: RS485
• Voltage - Supply: 3.3V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 25 Mbps
• Supply Current: 120 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• No. Of Channels: 4
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: BGA
• No. Of Pins: 176
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
The XR17V354 also provides the same RX FIFO data along with the LSR status information of each byte side-
by-side, at locations 0x0200 (channel 0), 0x0600 (channel 1), 0x0A00 (channel 2) and 0x0E00 (channel 3).
The entire RX data along with the status can be downloaded in a single PCI Burst Read operation of 32
DWORD reads. The Status and Data bytes must be read in 16 or 32 bits format to maintain data integrity. The
following tables show this clearly.
The TX FIFO data (up to the maximum 256 bytes) can be loaded in a single burst 32-bit write operation
(maximum 16 DWORD writes) at memory locations 0x0100 (channel 0), 0x0500 (channel 1), 0x0900 (channel
2) and 0x0D00 (channel 3).
2.1.2
2.1.3
Data Bit-31
Data Bit-31
WITH LSR
Read n+0 to n+1
Read n+2 to n+3
PCI Bus
Write n+0 to n+3
Write n+4 to n+7
PCI Bus
R
W
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
EAD
RITE
Etc.
RX FIFO,
Etc
Receive Data Byte n+1
TX FIFO
Receive Data Byte n+3
Tx FIFO Data Loading at locations 0x100, 0x500, 0x900 and 0xD00
Special Rx FIFO Data Unloading at locations 0x0200, 0x0600, 0x0A00 and 0x0E00
E
RRORS
Channel 0 to 3 Receive Data with Line Status Register in 32-bit alignment through the Configuration
FIFO Data n+1
FIFO Data n+3
FIFO Data n+3
FIFO Data n+7
Channel 0 to 3 Receive Data in 32-bit alignment through the Configuration Register Address
B
B
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
YTE
YTE
Line Status Register n+1
3
3
Receive Data Byte n+2
Register Address 0x0200, 0x0600, 0x0A00 and 0x0E00
0x0100, 0x0500, 0x0900 and 0x0D00
FIFO Data n+2
FIFO Data n+6
LSR n+1
LSR n+3
B
B
YTE
YTE
30
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
2
2
Receive Data Byte n+1
Receive Data Byte n+0
FIFO Data n+0
FIFO Data n+2
FIFO Data n+1
FIFO Data n+5
B
B
YTE
YTE
1
1
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
Line Status Register n+0
Receive Data Byte n+0
FIFO Data n+0
FIFO Data n+4
LSR n+0
LSR n+2
B
B
YTE
YTE
REV. 1.0.1
Data Bit-0
Data Bit-0
PCI Bus
0
PCI Bus
0