XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 15

• Manufacturer Part Number: XQ2V1000-4BG575N
• Description: FPGA 650MHZ CMOS1.5V 575-P
• Manufacturer: Xilinx Inc
• Series: QPro™ Virtex™-IIr

Specifications of XQ2V1000-4BG575N

• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 328
• Number Of Gates: 100000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 575-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: Q5801737

Digitally Controlled Impedance (DCI)
Today’s chip output signals with fast edge rates require
termination to prevent reflections and maintain signal
integrity. High pin count packages (especially ball grid arrays)
can not accommodate external termination resistors.
Virtex-II XCITE DCI provides controlled impedance drivers
and on-chip termination for single-ended and differential
I/Os. This eliminates the need for external resistors, and
improves signal integrity. The DCI feature can be used on
any IOB by selecting one of the DCI I/O standards.
When applied to inputs, DCI provides input parallel
termination. When applied to outputs, DCI provides
controlled impedance drivers (series termination) or output
parallel termination.
DCI operates independently on each I/O bank. When a DCI
I/O standard is used in a particular I/O bank, external
reference resistors must be connected to two dual-function
pins on the bank. These resistors, the voltage reference of
the N transistor (VRN), and the voltage reference of the P
transistor (VRP) are shown in
X-Ref Target - Figure 10
When used with a terminated I/O standard, the value of
resistors are specified by the standard (typically 50 Ω).
When used with a controlled impedance driver, the resistors
set the output impedance of the driver within the specified
range (25 Ω to 100 Ω). For all series and parallel
terminations listed in
resistors must have the same value for any given bank. One
percent resistors are recommended.
The DCI system adjusts the I/O impedance to match the two
external reference resistors or half of the reference
resistors, and compensates for impedance changes due to
voltage and/or temperature fluctuations. The adjustment is
done by turning parallel transistors in the IOB on or off.
DS122 (v2.0) December 21, 2007
Product Specification
Figure 10: DCI in a Virtex-II Bank
R
1 Bank
DCI
DCI
DCI
DCI
Table 11
VRN
VRP
Figure
and
V CCO
GND
Table
DS031_50_101200
10.
R
R
REF
REF
12, the reference
(1%)
(1%)
www.xilinx.com
Controlled Impedance Drivers
(Series Termination)
DCI can be used to provide a buffer with a controlled output
impedance. It is desirable for this output impedance to
match the transmission line impedance (Z). Virtex-II input
buffers also support LVDCI and LVDCI_DV2 I/O standards.
X-Ref Target - Figure 11
Table 11: SelectI/O-Ultra Controlled Impedance Buffers
Controlled Impedance Drivers
(Parallel Termination)
DCI also provides on-chip termination for SSTL3, SSTL2,
HSTL (Class I, II, III, or IV), and GTL/GTLP receivers or
transmitters on bidirectional lines.
Table 12
Virtex-II devices. V
Note that there is a V
GTLP_DCI, due to the on-chip termination resistor.
Table 12: SelectI/O-Ultra Buffers with On-Chip Parallel
Termination
Notes:
1.
SSTL3 Class II
SSTL2 Class II
HSTL Class IV
HSTL Class III
SSTL3 Class I
SSTL2 Class I
Virtex-II DCI
HSTL Class II
I/O Standard
SSTL Compatible
HSTL Class I
V
3.3 V
2.5 V
1.8 V
1.5 V
Z
CCO
GTLP
GTL
lists the on-chip parallel terminations available in
Figure 11: Internal Series Termination
IOB
V
CCO
CCO
CCO
LVDCI_33
LVDCI_25
LVDCI_18
LVDCI_15
= 3.3 V, 2.5 V, 1.8 V or 1.5 V
QPro Virtex-II 1.5V Platform FPGAs
must be set according to
DCI
Termination
requirement for GTL_DCI and
External
SSTL3_II
SSTL2_II
HSTL_IV
SSTL3_I
SSTL2_I
HSTL_III
HSTL_II
HSTL_I
GTLP
GTL
Z
DCI Half Impedance
LVDCI_DV2_33
LVDCI_DV2_25
LVDCI_DV2_18
LVDCI_DV2_15
SSTL3_II_DCI
SSTL2_II_DCI
SSTL3_I_DCI
SSTL2_I_DCI
HSTL_III_DCI
HSTL_IV_DCI
HSTL_II_DCI
Termination
HSTL_I_DCI
GTLP_DCI
GTL_DCI
On-Chip
DS031_51_110600
Table
8.
(1)
(1)
(1)
(1)
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