XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 62

• Manufacturer Part Number: XQ2V1000-4BG575N
• Description: FPGA 650MHZ CMOS1.5V 575-P
• Manufacturer: Xilinx Inc
• Series: QPro™ Virtex™-IIr

Specifications of XQ2V1000-4BG575N

• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 328
• Number Of Gates: 100000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 575-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: Q5801737

Table 44: Standard Capacitive Loads
DS122 (v2.0) December 21, 2007
Product Specification
Notes:
1.
2.
3.
LVTTL Fast Slew Rate, 2 mA drive
LVTTL Fast Slew Rate, 4 mA drive
LVTTL Fast Slew Rate, 6 mA drive
LVTTL Fast Slew Rate, 8 mA drive
LVTTL Fast Slew Rate, 12 mA drive
LVTTL Fast Slew Rate, 16 mA drive
LVTTL Fast Slew Rate, 24 mA drive
LVTTL Slow Slew Rate, 2 mA drive
LVTTL Slow Slew Rate, 4 mA drive
LVTTL Slow Slew Rate, 6 mA drive
LVTTL Slow Slew Rate, 8 mA drive
LVTTL Slow Slew Rate, 12 mA drive
LVTTL Slow Slew Rate, 16 mA drive
LVTTL Slow Slew Rate, 24 mA drive
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI 33 MHZ 3.3V
PCI 66 MHz 3.3V
PCI–X 133 MHz 3.3V
GTL
GTLP
HSTL Class I
HSTL Class II
HSTL Class III
HSTL Class IV
SSTL2 Class I
SSTL2 Class II
SSTL3 Class I
SSTL3 Class II
AGP
♦ Model the output in an IBIS simulation into the standard capacitive load.
♦ Record the relative time to the VOH or VOL transition of interest.
♦ Remove the capacitance, and model the actual PCB traces (transmission lines) and actual loads from the appropriate IBIS models
♦ Record the results from the new simulation.
♦ Compare with the capacitance simulation. The increase or decrease in delay from the capacitive load delay simulation should be
I/O parameter measurements are made with the capacitance values shown above.
I/O standard measurements are reflected in the IBIS model information except where the IBIS format precludes it.
Use of IBIS models results in a more accurate prediction of the propagation delay:
for driven devices.
added or subtracted from the value above to predict the actual delay.
R
Standard
www.xilinx.com
QPro Virtex-II 1.5V Platform FPGAs
Csl (pF)
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
10
10
10
10
10
10
10
10
10
10
10
10
0
0
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