XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 39

• Manufacturer Part Number: XQ2V1000-4BG575N
• Description: FPGA 650MHZ CMOS1.5V 575-P
• Manufacturer: Xilinx Inc
• Series: QPro™ Virtex™-IIr

Specifications of XQ2V1000-4BG575N

• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 328
• Number Of Gates: 100000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 575-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: Q5801737

Phase Shifting
The DCM provides additional control over clock skew
through either coarse- or fine-grained phase shifting. The
CLK0, CLK90, CLK180, and CLK270 outputs are each
phase shifted by ¼ of the input clock period relative to each
other, providing coarse phase control. Note that CLK90 and
CLK270 are not available in high-frequency mode.
Fine-phase adjustment affects all nine DCM output clocks.
When activated, the phase shift between the rising edges of
CLKIN and CLKFB is a specified fraction of the input clock
period.
In variable mode, the PHASE_SHIFT value can also be
dynamically incremented or decremented as determined by
PSINCDEC synchronously to PSCLK, when the PSEN
input is active.
shifting. For more information on DCM features, see
Table 26
variable mode.
Table 26: Fine-Phase Shifting Control Pins
Two separate components of the phase shift range must be
understood:
•
•
X-Ref Target - Figure 47
DS122 (v2.0) December 21, 2007
Product Specification
PSINCDEC
PSEN
PSCLK
PSDONE
Control Pin
PHASE_SHIFT attribute range
FINE_SHIFT_RANGE DCM timing parameter range
lists fine-phase shifting control pins, when used in
CLKOUT_PHASE_SHIFT
= NONE
CLKOUT_PHASE_SHIFT
= FIXED
CLKOUT_PHASE_SHIFT
= VARIABLE
R
Figure 47
Direction
out
in
in
in
illustrates the effects of fine-phase
CLKIN
CLKFB
CLKIN
CLKFB
CLKIN
CLKFB
Increment or decrement
Active when completed
Enable ± phase shift
Clock for phase shift
Function
Figure 47: Fine-Phase Shifting Effects
(PS/256) x PERIOD CLKIN
(PS negative)
[Ref
(PS/256) x PERIOD CLKIN
www.xilinx.com
(PS negative)
1].
The PHASE_SHIFT attribute is the numerator in the
following equation:
The full range of this attribute is always -255 to +255, but its
practical range varies with CLKIN frequency, as constrained
by the FINE_SHIFT_RANGE component, which represents
the total delay achievable by the phase shift delay line. Total
delay is a function of the number of delay taps used in the
circuit. Across process, voltage, and temperature, this
absolute range is guaranteed to be as specified under
"DCM Timing
Absolute range (fixed mode) = ± FINE_SHIFT_RANGE
Absolute range (variable mode) = ±
FINE_SHIFT_RANGE/2
The reason for the difference between fixed and variable
modes is as follows. For variable mode to allow symmetric,
dynamic sweeps from –255/256 to +255/256, the DCM sets
the "zero phase skew" point as the middle of the delay line,
thus dividing the total delay line range in half. In fixed mode,
since the PHASE_SHIFT value never changes after
configuration, the entire delay line is available for insertion
into either the CLKIN or CLKFB path (to create either
positive or negative skew).
Taking both of these components into consideration, the
following are some usage examples:
•
•
•
Phase Shift (ns) =
(PHASE_SHIFT/256)
If PERIOD
PHASE_SHIFT in fixed mode is limited to ± 128, and in
variable mode it is limited to ± 64.
If PERIOD
PHASE_SHIFT in fixed mode is limited to ± 255, and in
variable mode it is limited to ± 128.
If PERIOD
PHASE_SHIFT is limited to ± 255 in either mode.
(PS/256) x PERIOD CLKIN
Parameters".
(PS positive)
CLKIN
CLKIN
CLKIN
(PS/256) x PERIOD CLKIN
(PS positive)
= 2
= FINE_SHIFT_RANGE, then
≤ 0.5
QPro Virtex-II 1.5V Platform FPGAs
×
×
×
FINE_SHIFT_RANGE, then
PERIOD
FINE_SHIFT_RANGE, then
DS031_48_101201
CLKIN
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