XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 30

• Manufacturer Part Number: XQ2V1000-4BG575N
• Description: FPGA 650MHZ CMOS1.5V 575-P
• Manufacturer: Xilinx Inc
• Series: QPro™ Virtex™-IIr

Specifications of XQ2V1000-4BG575N

• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 328
• Number Of Gates: 100000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 575-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: Q5801737

Table 19: Dual-Port Mode Configurations
X-Ref Target - Figure 31
Port Aspect Ratios
Table 20
18 Kbit block SelectRAM. Virtex-II block SelectRAM also
includes dedicated routing resources to provide an efficient
interface with CLBs, block SelectRAM, and multipliers.
Table 20: 18 Kbit Block SelectRAM Port Aspect Ratio
DS122 (v2.0) December 21, 2007
Product Specification
Figure 31: 18 Kbit Block SelectRAM in Dual-Port Mode
Width
18
36
1
2
4
9
Port A
Port B
Port A
Port B
Port A
Port B
Port A
Port B
Port A
Port B
Port A
Port B
shows the depth and the width aspect ratios for the
16,384
Depth
8,192
4,096
2,048
1,024
512
R
DIB
DIPA
ADDRA
WEA
ENA
SSRA
DIPB
ADDRB
WEB
ENB
SSRB
DIA
Address Bus
CLKA
CLKB
ADDR[13:0]
ADDR[12:0]
ADDR[11:0]
ADDR[10:0]
512 x 36
512 x 36
18 Kbit Block SelectRAM
16K x 1
16K x 1
1K x 18
1K x 18
ADDR[9:0]
ADDR[8:0]
8K x 2
8K x 2
4K x 4
4K x 4
2K x 9
2K x 9
DATA[15:0]
DATA[31:0]
Data Bus
DATA[1:0]
DATA[3:0]
DATA[7:0]
DATA[0]
DOPA
DOPB
512 x 36
16K x 1
1K x 18
1K x 18
8K x 2
8K x 2
4K x 4
4K x 4
2K x 9
2K x 9
DOA
DOB
DS031_11_071602
Parity Bus
Parity[1:0]
Parity[3:0]
Parity[0]
N/A
N/A
N/A
www.xilinx.com
512 x 36
16K x 1
1K x 18
4K x 4
8K x 2
2K x 9
4K x 4
2K x 9
Read/Write Operations
The Virtex-II block SelectRAM read operation is fully
synchronous. An address is presented, and the read
operation is enabled by control signals WEA and WEB in
addition to ENA or ENB. Then, depending on clock polarity,
a rising or falling clock edge causes the stored data to be
loaded into output registers.
The write operation is also fully synchronous. Data and
address are presented, and the write operation is enabled
by control signals WEA or WEB in addition to ENA or ENB.
Then, again depending on the clock input mode, a rising or
falling clock edge causes the data to be loaded into the
memory cell addressed.
A write operation performs a simultaneous read operation.
Three different options are available, selected by configuration:
•
•
•
WRITE_FIRST
The WRITE_FIRST option is a transparent mode. The
same clock edge that writes the data input (DI) into the
memory also transfers DI into the output registers DO
as shown in
READ_FIRST
The READ_FIRST option is a read-before-write mode.
The same clock edge that writes data input (DI) into the
memory also transfers the prior content of the memory
cell addressed into the data output registers DO, as
shown in
NO_CHANGE
The NO_CHANGE option maintains the content of the
output registers, regardless of the write operation. The
clock edge during the write mode has no effect on the
content of the data output register DO. When the port is
configured as NO_CHANGE, only a read operation
loads a new value in the output register DO, as shown in
Figure 34, page
512 x 36
16K x 1
1K x 18
2K x 9
8K x 2
4K x 4
Figure 33, page
Figure 32, page
31.
QPro Virtex-II 1.5V Platform FPGAs
512 x 36
16K x 1
1K x 18
8K x 2
31.
31.
512 x 36
16K x 1
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