XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 19

• Manufacturer Part Number: XQ2V1000-4BG575N
• Description: FPGA 650MHZ CMOS1.5V 575-P
• Manufacturer: Xilinx Inc
• Series: QPro™ Virtex™-IIr

Specifications of XQ2V1000-4BG575N

• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 328
• Number Of Gates: 100000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 575-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: Q5801737

Configurable Logic Blocks (CLBs)
The Virtex-II configurable logic blocks (CLB) are organized in
an array and are used to build combinatorial and
synchronous logic designs. Each CLB element is tied to a
switch matrix to access the general routing matrix, as shown
in
with fast local feedback within the CLB. The four slices are
split into two columns of two slices with two independent
carry logic chains and one common shift chain.
X-Ref Target - Figure 15
Slice Description
Each slice includes two 4-input function generators, carry
logic, arithmetic logic gates, wide function multiplexers and
two storage elements. As shown in
function generator is programmable as a 4-input LUT, 16
bits of distributed SelectRAM memory, or a 16-bit variable-
tap shift register element.
X-Ref Target - Figure 16
The output from the function generator in each slice drives
both the slice output and the D input of the storage element.
Figure 17
DS122 (v2.0) December 21, 2007
Product Specification
Figure
Switch
Matrix
RAM16
RAM16
15. A CLB element comprises four similar slices
Figure 16: Virtex-II Slice Configuration
shows a more detailed view of a single slice.
R
Figure 15: Virtex-II CLB Element
SRL16
SRL16
LUT
LUT
TBUF X0Y1
TBUF X0Y0
G
F
X0Y1
X0Y0
Slice
Slice
COUT
Arithmetic Logic
CIN
MUXF5
MUXFx
CY
CY
ORCY
SHIFT
X1Y1
X1Y0
Slice
Slice
COUT
Figure
CIN
Register
Register
DS031_31_100900
16, each 4-input
Fast
Connects
to neighbors
DS031_32_101600
www.xilinx.com
Configurations
Look-Up Table
Virtex-II function generators are implemented as 4-input
look-up tables (LUTs). Four independent inputs are
provided to each of the two function generators in a slice (F
and G). These function generators are each capable of
implementing any arbitrarily defined Boolean function of
four inputs. The propagation delay is therefore independent
of the function implemented. Signals from the function
generators can exit the slice (X or Y output), can input the
XOR dedicated gate (see arithmetic logic), or input the
carry-logic multiplexer (see fast look-ahead carry logic), or
feed the D input of the storage element, or go to the MUXF5
(not shown in
In addition to the basic LUTs, the Virtex-II slice contains
logic (MUXF5 and MUXFX multiplexers) that combines
function generators to provide any function of five, six,
seven, or eight inputs. The MUXFXs are either MUXF6,
MUXF7, or MUXF8 according to the slice considered in the
CLB. Selected functions up to nine inputs (MUXF5
multiplexer) can be implemented in one slice. The MUXFX
can also be a MUXF6, MUXF7, or MUXF8 multiplexer to
map any functions of six, seven, or eight inputs and selected
wide logic functions.
Register/Latch
The storage elements in a Virtex-II slice can be configured
as either edge-triggered D-type flip-flops or level-sensitive
latches. The D input can be directly driven by the X or Y
output via the DX or DY input, or by the slice inputs
bypassing the function generators via the BX or BY input.
The clock enable signal (CE) is active High by default. If left
unconnected, the clock enable for that storage element
defaults to the active state.
In addition to clock (CK) and clock enable (CE) signals,
each slice has set and reset signals (SR and BY slice
inputs). SR forces the storage element into the state
specified by the attribute SRHIGH or SRLOW. SRHIGH
forces a logic “1” when SR is asserted. SRLOW forces a
logic “0”. When SR is used, a second input (BY) forces the
storage element into the opposite state. The reset condition
is predominant over the set condition
The initial state after configuration or global initial state is
defined by a separate INIT0 and INIT1 attribute. By default,
setting the SRLOW attribute sets INIT0, and setting the
SRHIGH attribute sets INIT1.
For each slice, set and reset can be set to be synchronous
or asynchronous. Virtex-II devices also have the ability to
set INIT0 and INIT1 independent of SRHIGH and SRLOW.
Control signals CLK, CE, and SR are common to both
storage elements in one slice. All control signals have
independent polarities. Any inverter placed on a control input
is automatically absorbed.
Figure 17, page
QPro Virtex-II 1.5V Platform FPGAs
20).
(Figure 18, page
21).
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