XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 2

• Manufacturer Part Number: XQ2V1000-4BG575N
• Description: FPGA 650MHZ CMOS1.5V 575-P
• Manufacturer: Xilinx Inc
• Series: QPro™ Virtex™-IIr

Specifications of XQ2V1000-4BG575N

• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 328
• Number Of Gates: 100000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 575-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: Q5801737

•
General Description
The Virtex-II family includes platform FPGAs developed for
high performance from low-density to high-density designs
that are based on IP cores and customized modules. The
family delivers complete solutions for telecommunication,
wireless, networking, video, and DSP applications,
including PCI, LVDS, and DDR interfaces.
The leading-edge 0.15 µm/0.12 µm CMOS 8-layer metal
process and the Virtex-II architecture are optimized for high
Table 1: Virtex-II Field-Programmable Gate Array Family Members
Packaging
Offerings include ball grid array (BGA) packages with
1.00 mm and 1.27 mm pitches. In addition to traditional
wire-bond interconnects, flip-chip interconnect is used in
some of the CGA offerings. The use of flip-chip interconnect
offers more I/Os than is possible in wire-bond versions of
the similar packages. Flip-chip construction offers the
combination of high pin count with high thermal capacity.
Table 2
The Virtex-II device/package combination table
DS122 (v2.0) December 21, 2007
Product Specification
Notes:
1.
XQ2V1000
XQ2V3000
XQ2V6000
Device
SRAM-based in-system configuration
♦
♦
♦
♦
See details in
shows the maximum number of user I/Os available.
Fast SelectMAP configuration
Triple Data Encryption Standard (DES) security
option (Bitstream Encryption)
IEEE 1532 support
Partial reconfiguration
R
System
Table 2
Gates
1M
3M
6M
.
Row x Col.
40 x 32
64 x 56
96 x 88
(1 CLB = 4 slices = Max 128 bits)
Array
Slices
14,336
33,792
5,120
CLB
(Table 5,
Distributed
RAM Kbits
Maximum
www.xilinx.com
1,056
160
448
•
•
•
speed with low power consumption. Combining a wide
variety of flexible features and a large range of densities up
to 8 million system gates, the Virtex-II family enhances
programmable logic design capabilities and is a powerful
alternative to mask-programmed gates arrays. As shown in
Table
ranging from 1M to 6M system gates.
page
device and package using wire-bond or flip-chip technology.
Table 2: Maximum Number of User I/O Pads
XQ2V1000
XQ2V3000
XQ2V6000
Multiplier
♦
♦
0.15 µm 8-layer metal process with 0.12 µm high-
speed transistors
1.5V (V
V
IEEE 1149.1 compatible Boundary-Scan logic support
Blocks
CCAUX
6) details the maximum number of I/Os for each
1, the QPro Virtex-II family comprises three members,
144
40
96
Device
Unlimited reprogrammability
Readback capability
CCINT
auxiliary and V
) core power supply, dedicated 3.3V
18 Kbit
Blocks
SelectRAM Blocks
144
40
96
QPro Virtex-II 1.5V Platform FPGAs
Wire-Bond
CCO
Max RAM
(Kbits)
328
516
1,728
2,592
–
720
I/O power supplies
DCMs
12
12
8
Flip-Chip
824
–
–
Max I/O
Pads
1,104
432
720
(1)
2