XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 72

• Manufacturer Part Number: XQ2V1000-4BG575N
• Description: FPGA 650MHZ CMOS1.5V 575-P
• Manufacturer: Xilinx Inc
• Series: QPro™ Virtex™-IIr

Specifications of XQ2V1000-4BG575N

• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 328
• Number Of Gates: 100000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 575-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: Q5801737

Output Clock Jitter
Table 60: Output Clock Jitter
Output Clock Phase Alignment
Table 61: Output Clock Phase Alignment
DS122 (v2.0) December 21, 2007
Product Specification
Notes:
1.
Notes:
1.
2.
3.
Clock Synthesis Period Jitter
Phase Offset Between CLKIN and CLKFB
Phase Offset Between Any DCM Outputs
Duty Cycle Precision
CLK0
CLK90
CLK180
CLK270
CLK2X, CLK2X180
CLKDV (integer division)
CLKDV (non-integer division)
CLKFX, CLKFX180
CLKIN/CLKFB
All CLK* outputs
DLL outputs
CLKFX outputs
Values for this parameter are available at http://www.xilinx.com.
The term DLL outputs is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if DUTY_CYCLE_CORRECTION
= TRUE.
Specification also applies to PSCLK.
R
(1)
Description
Description
CLKOUT_PHASE
CLKOUT_PER_JITT_0
CLKOUT_PER_JITT_90
CLKOUT_PER_JITT_180
CLKOUT_PER_JITT_270
CLKOUT_PER_JITT_2X
CLKOUT_PER_JITT_DV1
CLKOUT_PER_JITT_DV2
CLKOUT_PER_JITT_FX
CLKIN_CLKFB_PHASE
CLKOUT_DUTY_CYCLE_DLL
CLKOUT_DUTY_CYCLE_FX
www.xilinx.com
Symbol
Symbol
(2)
Constraints
Constraints
QPro Virtex-II 1.5V Platform FPGAs
Note 1
±100
±150
±150
±150
±200
±150
±300
±140
±150
±100
Speed Grade
Speed Grade
±50
-5
-5
Note 1
±100
±150
±150
±150
±200
±150
±300
±140
±150
±100
±50
-4
-4
Units
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
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