XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 33

• Manufacturer Part Number: XQ2V1000-4BG575N
• Description: FPGA 650MHZ CMOS1.5V 575-P
• Manufacturer: Xilinx Inc
• Series: QPro™ Virtex™-IIr

Specifications of XQ2V1000-4BG575N

• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 328
• Number Of Gates: 100000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 575-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: Q5801737

18-Bit x 18-Bit Multipliers
Introduction
A Virtex-II multiplier block is an 18-bit by 18-bit 2’s
complement signed multiplier. Virtex-II devices incorporate
many embedded multiplier blocks. These multipliers can be
associated with an 18 Kbit block SelectRAM resource or
can be used independently. They are optimized for high-
speed operations and have a lower power consumption
compared to an 18-bit x 18-bit multiplier in slices.
Each SelectRAM memory and multiplier block is tied to four
switch matrices, as shown in
X-Ref Target - Figure 36
Association with Block SelectRAM Memory
The interconnect is designed to allow SelectRAM memory
and multiplier blocks to be used at the same time, but some
interconnect is shared between the SelectRAM and the
multiplier. Thus, SelectRAM memory can be used only up to
18 bits wide when the multiplier is used, because the
multiplier shares inputs with the upper data bits of the
SelectRAM memory.
This sharing of the interconnect is optimized for an 18-bit-
wide block SelectRAM resource feeding the multiplier. The
DS122 (v2.0) December 21, 2007
Product Specification
Figure 36: SelectRAM and Multiplier Blocks
Switch
Switch
Switch
Switch
Matrix
Matrix
Matrix
Matrix
R
18-Kbit block
SelectRAM
Figure
36.
DS031_33_101000
www.xilinx.com
use of SelectRAM memory and the multiplier with an
accumulator in LUTs allows for implementation of a digital
signal processor (DSP) multiplier-accumulator (MAC)
function, which is commonly used in finite and infinite
impulse response (FIR and IIR) digital filters.
Configuration
The multiplier block is an 18-bit by 18-bit signed multiplier
(2's complement). Both A and B are 18-bit-wide inputs, and
the output is 36 bits.
X-Ref Target - Figure 37
Locations/Organization
Multiplier organization is identical to the 18 Kbit SelectRAM
organization, because each multiplier is associated with an
18 Kbit block SelectRAM resource.
In addition to the built-in multiplier blocks, the CLB elements
have dedicated logic to implement efficient multipliers in
logic (refer to
Table 24: Multiplier Floor Plan
A[17:0]
B[17:0]
XQ2V1000
XQ2V3000
XQ2V6000
Device
"Configurable Logic Blocks (CLBs)," page
Figure 37: Multiplier Block
Columns
Figure 37
QPro Virtex-II 1.5V Platform FPGAs
4
6
6
MULT 18 x 18
Multiplier Block
shows a multiplier block.
Per Column
10
16
24
Multipliers
DS031_40_100400
Total
144
40
96
P[35:0]
19).
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