XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 5
XQ2V1000-4BG575N
Manufacturer Part Number
XQ2V1000-4BG575N
Description
FPGA 650MHZ CMOS1.5V 575-P
Manufacturer
Xilinx Inc
Series
QPro™ Virtex™-IIr
Datasheet
1.XQ2V1000-4BG575N.pdf
(134 pages)
Specifications of XQ2V1000-4BG575N
Number Of Labs/clbs
1280
Total Ram Bits
737280
Number Of I /o
328
Number Of Gates
100000
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-55°C ~ 125°C
Package / Case
575-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Other names
Q5801737
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XQ2V1000-4BG575N
Manufacturer:
XILINX
Quantity:
325
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Routing Resources
The IOB, CLB, block SelectRAM, multiplier, and DCM
elements all use the same interconnect scheme and the
same access to the global routing matrix. Timing models
are shared, greatly improving the predictability of the
performance of high-speed designs.
There are a total of 16 global clock lines with eight available
per quadrant. In addition, 24 vertical and horizontal long lines
per row or column as well as massive secondary and local
routing resources provide fast interconnect. Virtex-II buffered
interconnects are relatively unaffected by net fanout, and the
interconnect layout is designed to minimize crosstalk.
Horizontal and vertical routing resources for each row or
column include:
•
•
•
•
DS122 (v2.0) December 21, 2007
Product Specification
24 long lines
120 hex lines
40 double lines
16 direct connect lines (total in all four directions)
R
www.xilinx.com
Boundary-Scan
Boundary-Scan instructions and associated data registers
support a standard methodology for accessing and
configuring Virtex-II devices that complies with IEEE
standards 1149.1 — 1993 and 1532. A system mode and a
test mode are implemented. In system mode, a Virtex-II
device performs its intended mission even while executing
non-test boundary-scan instructions. In test mode,
boundary-scan test instructions control the I/O pins for
testing purposes. The Virtex-II Test Access Port (TAP)
supports BYPASS, PRELOAD, SAMPLE, IDCODE, and
USERCODE non-test instructions. The EXTEST, INTEST,
and HIGHZ test instructions are also supported.
QPro Virtex-II 1.5V Platform FPGAs
5
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