XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 9

• Manufacturer Part Number: XQ2V1000-4BG575N
• Description: FPGA 650MHZ CMOS1.5V 575-P
• Manufacturer: Xilinx Inc
• Series: QPro™ Virtex™-IIr

Specifications of XQ2V1000-4BG575N

• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 328
• Number Of Gates: 100000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 575-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: Q5801737

Table 8: Supported DCI I/O Standards
Logic Resources
IOB blocks include six storage elements, as shown in
X-Ref Target - Figure 3
DS122 (v2.0) December 21, 2007
Product Specification
Notes:
1.
2.
LVDCI_33
LVDCI_DV2_33
LVDCI_25
LVDCI_DV2_25
LVDCI_18
LVDCI_DV2_18
LVDCI_15
LVDCI_DV2_15
GTL_DCI
GTLP_DCI
HSTL_I_DCI
HSTL_II_DCI
HSTL_III_DCI
HSTL_IV_DCI
HSTL_I_DCI
HSTL_II_DCI
HSTL_III_DCI
HSTL_IV_DCI
SSTL2_I_DCI
SSTL2_II_DCI
SSTL3_I_DCI
SSTL3_II_DCI
LVDCI_XX and LVDCI_DV2_XX are LVCMOS controlled
impedance buffers, matching the reference resistors or half of
the reference resistors.
These are SSTL compatible.
Standard
I/O
OCK1
OCK2
OCK1
OCK2
Reg
Reg
Reg
Reg
(1)
(1)
(1)
(1)
R
(2)
(2)
(2)
(2)
Figure 3: Virtex-II IOB Block
(1)
(1)
(1)
(1)
DDR mux
DDR mux
3-State
Output
Output
V
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.5
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
2.5
2.5
3.3
3.3
CCO
Input
V
N/A
N/A
N/A
N/A
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.5
1.5
1.5
1.5
1.5
2.5
2.5
3.3
3.3
CCO
IOB
Input
V
0.75
0.75
1.25
1.25
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.8
1.0
0.9
0.9
0.9
0.9
1.1
1.1
1.5
1.5
REF
ICK1
ICK2
Reg
Reg
Input
Termination
PAD
DS031_29_100900
Series
Series
Series
Series
Series
Series
Series
Series
Single
Single
Single
Single
Single
Single
Type
Split
Split
Split
Split
Split
Split
Split
Split
Figure
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3.
Each storage element can be configured either as an edge-
triggered D-type flip-flop or as a level-sensitive latch. On the
input, output, and 3-state path, one or two DDR registers
can be used.
Double data rate is directly accomplished by the two
registers on each path, clocked by the rising edges (or
falling edges) from two different clock nets. The two clock
signals are generated by the DCM and must be 180
degrees out of phase, as shown in
are two input, output, and 3-state data signals, each being
alternately clocked out.
The DDR mechanism shown in
mirror a copy of the clock on the output. This is useful for
propagating a clock along the data that has an identical delay.
It is also useful for multiple clock generation, where there is a
unique clock driver for every clock load. Virtex-II devices can
produce many copies of a clock with very little skew.
Each group of two registers has a clock enable signal (ICE
for the input registers, OCE for the output registers, and
TCE for the 3-state registers). The clock enable signals are
active High by default. If left unconnected, the clock enable
for that storage element defaults to the active state.
Each IOB block has common synchronous or asynchronous
set and reset (SR and REV signals).
SR forces the storage element into the state specified by
the SRHIGH or SRLOW attribute. SRHIGH forces a logic
“1”. SRLOW forces a logic “0”. When SR is used, a second
input (REV) forces the storage element into the opposite
state. The reset condition predominates over the set
condition. The initial state after configuration or global
initialization state is defined by a separate INIT0 and INIT1
attribute. By default, the SRLOW attribute forces INIT0, and
the SRHIGH attribute forces INIT1.
For each storage element, the SRHIGH, SRLOW, INIT0,
and INIT1 attributes are independent. Synchronous or
asynchronous set/reset is consistent in an IOB block.
All the control signals have independent polarities. Any
inverter placed on a control input is automatically absorbed.
Each register or latch (independent of all other registers or
latches) (see
•
•
•
•
•
•
•
The synchronous reset overrides a set, and an
asynchronous clear overrides a preset.
No set or reset
Synchronous set
Synchronous reset
Synchronous set and reset
Asynchronous set (preset)
Asynchronous reset (clear)
Asynchronous set and reset (preset and clear)
Figure 5, page
QPro Virtex-II 1.5V Platform FPGAs
10) can be configured as follows:
Figure 4
Figure 4, page
can be used to
10. There
9