XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 41

• Manufacturer Part Number: XQ2V1000-4BG575N
• Description: FPGA 650MHZ CMOS1.5V 575-P
• Manufacturer: Xilinx Inc
• Series: QPro™ Virtex™-IIr

Specifications of XQ2V1000-4BG575N

• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 328
• Number Of Gates: 100000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 575-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: Q5801737

Active Interconnect Technology
Local and global Virtex-II routing resources are optimized
for speed and timing predictability, as well as to facilitate IP
cores implementation. Virtex-II Active Interconnect
Technology is a fully buffered programmable routing matrix.
All routing resources are segmented to offer the advantages
of a hierarchical solution. Virtex-II logic features like CLBs,
IOBs, block RAM, multipliers, and DCMs are all connected
to an identical switch matrix for access to global routing
resources, as shown in
X-Ref Target - Figure 48
X-Ref Target - Figure 49
DS122 (v2.0) December 21, 2007
Product Specification
R
Switch
Switch
Switch
Switch
Switch
Matrix
Matrix
Matrix
Matrix
Matrix
Figure
IOB
IOB
IOB
IOB
IOB
Switch
Switch
Switch
Matrix
Matrix
Matrix
48.
Switch
Switch
Switch
Switch
Switch
Matrix
Matrix
Matrix
Matrix
Matrix
Figure 48: Active Interconnect Technology
DCM
CLB
IOB
Figure 49: Routing Resources
CLB
CLB
CLB
CLB
IOB
www.xilinx.com
Switch
Switch
Switch
Switch
Switch
Matrix
Matrix
Matrix
Matrix
Matrix
Switch
Switch
Switch
Switch
Matrix
Matrix
Matrix
Matrix
Each Virtex-II device can be represented as an array of
switch matrices with logic blocks attached, as illustrated in
Figure
Place-and-route software takes advantage of this regular
array to deliver optimum system performance and fast
compile times. The segmented routing resources are
essential to guarantee IP cores portability and to efficiently
handle an incremental design flow that is based on modular
implementations. Total design time is reduced due to fewer
and shorter design iterations.
CLB
CLB
CLB
CLB
IOB
49.
BRAM
18Kb
Switch
Switch
Switch
Switch
Switch
Matrix
Matrix
Matrix
Matrix
Matrix
QPro Virtex-II 1.5V Platform FPGAs
DS031_55_101000
18 x 18
DCM
MULT
Switch
Switch
Switch
Switch
Switch
Matrix
Matrix
Matrix
Matrix
Matrix
DS031_34_110300
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