XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 68

• Manufacturer Part Number: XQ2V1000-4BG575N
• Description: FPGA 650MHZ CMOS1.5V 575-P
• Manufacturer: Xilinx Inc
• Series: QPro™ Virtex™-IIr

Specifications of XQ2V1000-4BG575N

• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 328
• Number Of Gates: 100000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 575-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: Q5801737

QPro Virtex-II Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DCM
Table 54: Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DCM
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DCM
Table 55: Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DCM
DS122 (v2.0) December 21, 2007
Product Specification
Notes:
1.
2.
3.
Notes:
1.
2.
LVTTL Global Clock Input to Output delay using Output flip-flop,
12 mA, Fast Slew Rate, with DCM. For data output with different
standards, adjust the delays with the values shown in
Switching Characteristics Standard Adjustments," page
Global Clock and OFF with DCM
LVTTL Global Clock Input to Output Delay using Output flip-flop,
12 mA, Fast Slew Rate, without DCM. For data output with different
standards, adjust the delays with the values shown in
Switching Characteristics Standard Adjustments," page
Global Clock and OFF without DCM
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
Output timing is measured with a 35 pF external capacitive load. The only time it is not 50% of V
standards and different loads, see
DCM output jitter is included in the measurement.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
Output timing is measured at 50% V
Table 43, page
R
61.
Description
Description
Table 43, page
CC
threshold with 35 pF external capacitive load. For other I/O standards and different loads, see
61.
"IOB Output
"IOB Output
58.
58.
www.xilinx.com
T
Symbol
ICKOFDCM
Symbol
T
ICKOF
XQ2V1000
XQ2V3000
XQ2V6000
XQ2V1000
XQ2V3000
XQ2V6000
Device
Device
QPro Virtex-II 1.5V Platform FPGAs
CC
threshold is with LVCMOS. For other I/O
1.28
1.28
1.88
4.28
4.43
5.38
-5
Speed Grade
Speed Grade
-5
1.48
1.48
2.17
4.62
5.10
5.93
-4
-4
Units
Units
ns
ns
ns
ns
ns
ns
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