AGL030V2-CSG81 Actel, AGL030V2-CSG81 Datasheet - Page 27

• Manufacturer Part Number: AGL030V2-CSG81
• Description: FPGA - Field Programmable Gate Array 30K System Gates IGLOO
• Manufacturer: Actel

Specifications of AGL030V2-CSG81

• Processor Series: AGL030
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 66
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 30 K
• Package / Case: CSP-81
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-18 • Different Components Contributing to Dynamic Power Consumption in IGLOO Devices
Parameter
PAC1
PAC2
PAC3
PAC4
PAC5
PAC6
PAC7
PAC8
PAC9
PAC10
PAC11
PAC12
PAC13
*
For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet
calculator or SmartPower tool in Actel Libero
Clock contribution of a
Global Rib
Clock contribution of a
Global Spine
Clock contribution of a
VersaTile row
Clock contribution of a
VersaTile
sequential module
First contribution of a
VersaTile
sequential module
Second contribution of a
VersaTile
sequential module
Contribution
VersaTile
combinatorial module
Average contribution of a
routing net
Contribution of an I/O
input
dependent)
Contribution of an I/O
output
dependent)
Average contribution of a
RAM block during a read
operation
Average contribution of a
RAM block during a write
operation
Dynamic
contribution
Power Consumption of Various Internal Resources
For IGLOO V2 or V5 Devices, 1.5 V DC Core Supply Voltage
Definition
pin
pin
used
used
used
used
(standard-
(standard-
of
as
as
as
as
PLL
a
a
a
a
a
AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015
14.48
2.48
®
See
See
Integrated Design Environment (IDE).
Table 2-12 on page 2-10
Table 2-15 on page 2-11
12.77
1.85
R ev i si o n 1 8
Device Specific Dynamic Power
12.77
1.58
11.03
1.58
(µW/MHz)
0.057
0.207
25.00
30.00
0.81
0.11
0.17
2.70
through
through
0.7
11.03
0.81
Table 2-17 on page
Table 2-14 on page
IGLOO Low Power Flash FPGAs
0.81
9.3
0.41
9.3
2-12.
2-11.
0.41
9.3
2- 13