AGL030V2-CSG81 Actel, AGL030V2-CSG81 Datasheet - Page 8

• Manufacturer Part Number: AGL030V2-CSG81
• Description: FPGA - Field Programmable Gate Array 30K System Gates IGLOO
• Manufacturer: Actel

Specifications of AGL030V2-CSG81

• Processor Series: AGL030
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 66
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 30 K
• Package / Case: CSP-81
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IGLOO Device Family Overview
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Flash Advantages
Low Power
Flash-based IGLOO devices exhibit power characteristics similar to those of an ASIC, making them an
ideal choice for power-sensitive applications. IGLOO devices have only a very limited power-on current
surge and no high-current transition period, both of which occur on many FPGAs.
IGLOO devices also have low dynamic power consumption to further maximize power savings; power is
even further reduced by the use of a 1.2 V core voltage.
Low dynamic power consumption, combined with low static power consumption and Flash*Freeze
technology, gives the IGLOO device the lowest total system power offered by any FPGA.
Security
The nonvolatile, flash-based IGLOO devices do not require a boot PROM, so there is no vulnerable
external bitstream that can be easily copied. IGLOO devices incorporate FlashLock, which provides a
unique combination of reprogrammability and design security without external overhead, advantages that
only an FPGA with nonvolatile flash programming can offer.
IGLOO devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed
intellectual property and configuration data. In addition, all FlashROM data in IGLOO devices can be
encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption
standard. AES was adopted by the National Institute of Standards and Technology (NIST) in 2000 and
replaces the 1977 DES standard. IGLOO devices have a built-in AES decryption engine and a flash-
based AES key that make them the most comprehensive programmable logic device security solution
available today. IGLOO devices with AES-based security allow for secure, remote field updates over
public networks such as the Internet, and ensure that valuable IP remains out of the hands of system
overbuilders, system cloners, and IP thieves. The contents of a programmed IGLOO device cannot be
read back, although secure design verification is possible.
Security, built into the FPGA fabric, is an inherent component of the IGLOO family. The flash cells are
located beneath seven metal layers, and many device design and layout techniques have been used to
make invasive attacks extremely difficult. The IGLOO family, with FlashLock and AES security, is unique
in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected and
secure, making remote ISP possible. An IGLOO device provides the most impenetrable security for
programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the
configuration data is an inherent part of the FPGA structure, and no external configuration data needs to
be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based IGLOO FPGAs do
not require system configuration components such as EEPROMs or microcontrollers to load device
configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system
reliability.
Live at Power-Up
The Actel flash-based IGLOO devices support Level 0 of the LAPU classification standard. This feature
helps in system component initialization, execution of critical tasks before the processor wakes up, setup
and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature
of flash-based IGLOO devices greatly simplifies total system design and reduces total system cost, often
eliminating the need for CPLDs and clock generation PLLs. In addition, glitches and brownouts in system
power will not corrupt the IGLOO device's flash configuration, and unlike SRAM-based FPGAs, the
device will not have to be reloaded when system power is restored. This enables the reduction or
complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock
generator devices from the PCB design. Flash-based IGLOO devices simplify total system design and
reduce cost and design risk while increasing system reliability and improving system initialization time.
IGLOO flash FPGAs allow the user to quickly enter and exit Flash*Freeze mode. This is done almost
instantly (within 1 µs) and the device retains configuration and data in registers and RAM. Unlike SRAM-
based FPGAs the device does not need to reload configuration and design state from external memory
components; instead it retains all necessary information to resume operation immediately.
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