OM13012,598 NXP Semiconductors, OM13012,598 Datasheet - Page 18

• Manufacturer Part Number: OM13012,598
• Description: BOARD EVAL LPC11C2X
• Manufacturer: NXP Semiconductors

Specifications of OM13012,598

• Featured Product: 32-bit ARM Cortex-M0 Microcontrollers
• Processor To Be Evaluated: LPC11C2x
• Data Bus Width: 32 bit
• Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-6645; OM13012

NXP Semiconductors
LPC11CX2_CX4
Product data sheet
7.8.1 Features
7.9.1 Features
7.10 I
7.9 SPI serial I/O controller
Support for RS-485/9-bit mode allows both software address detection and automatic
address detection using 9-bit mode.
The UART includes a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
The LPC11Cx2/Cx4 contain two SPI controllers. Both SPI controllers support SSP
features.
The SPI controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can
interact with multiple masters and slaves on the bus. Only a single master and a single
slave can communicate on the bus during a given data transfer. The SPI supports full
duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the
slave and from the slave to the master. In practice, often only one of these data flows
carries meaningful data.
The LPC11Cx2/Cx4 contain one I
The I
(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
C-bus serial I/O controller
Maximum UART data bit rate of 3.125 Mbit/s.
16 Byte Receive and Transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
FIFO control mechanism that enables software flow control implementation.
Support for RS-485/9-bit mode.
Support for modem control.
Maximum SPI speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode)
Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
2
C-bus is bidirectional for inter-IC control using only two wires: a Serial CLock line
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 3 December 2010
2
C-bus controller.
32-bit ARM Cortex-M0 microcontroller
LPC11Cx2/Cx4
© NXP B.V. 2010. All rights reserved.
18 of 61