OM13012,598 NXP Semiconductors, OM13012,598 Datasheet - Page 27

BOARD EVAL LPC11C2X

OM13012,598

Manufacturer Part Number
OM13012,598
Description
BOARD EVAL LPC11C2X
Manufacturer
NXP Semiconductors
Datasheet

Specifications of OM13012,598

Featured Product
32-bit ARM Cortex-M0 Microcontrollers
Processor To Be Evaluated
LPC11C2x
Data Bus Width
32 bit
Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-6645
OM13012
NXP Semiconductors
LPC11CX2_CX4
Product data sheet
7.17.6 APB interface
7.17.7 AHBLite
7.17.8 External interrupt inputs
7.18 Emulation and debugging
The C_CAN ISP command handler uses the CANopen protocol and data organization
method. C_CAN ISP commands have the same functionality as UART ISP commands.
The APB peripherals are located on one APB bus.
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the Boot ROM.
All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs
serve as external interrupts (see
Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four
breakpoints and two watchpoints is supported.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 3 December 2010
Section
7.17.1).
32-bit ARM Cortex-M0 microcontroller
LPC11Cx2/Cx4
© NXP B.V. 2010. All rights reserved.
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