DP83848VYB National Semiconductor, DP83848VYB Datasheet - Page 10

• Manufacturer Part Number: DP83848VYB
• Description: TRANSCEIVER, ENET PHY, 10/100, 48LQFP
• Manufacturer: National Semiconductor

Specifications of DP83848VYB

• Data Rate: 100Mbps
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3u
• Supply Current: 92mA
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +105°C
• Digital Ic Case Style: LQFP
• No.: RoHS Compliant
• Interface Type: MII Serial, RMII
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Not Compliant

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PHYAD0 (COL)
PHYAD1 (RXD1_0)
PHYAD2 (RXD0_1)
PHYAD3 (RXD1_2)
PHYAD4 (RXD1_3)
AN_EN(LED_ACT/COL)
AN_1 (LED_SPEED)
AN_0 (LED_LINK)
MII_MODE (RX_DV)
SNI_MODE (TXD_3)
1.7 STRAP OPTIONS
The DP83848VYB uses many of the functional pins as strap
options. The values of these pins are sampled during reset
and used to strap the device into specific modes of operation.
The strap option pin assignments are defined below. The
functional pin name is indicated in parentheses.
Signal Name
S, O, PU
S, O, PD
S, O, PU
S, O, PD
Type
Pin #
42
43
44
45
46
26
27
28
39
6
PHY ADDRESS [4:0]: The DP83848VYB provides five PHY address pins, the state of
which are latched into the PHYCTRL register at system Hardware-Reset.
The DP83848VYB supports PHY Address strapping values 0 (<00000>) through 31
(<11111>).A PHY Adress of 0 puts the part into the Mll isolate Mode. The Mll isolate
mode must be selected by strapping Phy Address 0; changing to Address 0 by register
write will not put the Phy in the Mll isolate mode. Please refer to section 2.3 PHY
ADDRESS for additional information.
PHYAD0 pin has weak internal pull-up resistor.
PHYAD[4:1] pins have weak internal pull-up resistors.
Auto-Negotiation Enable: When high, this enables Auto-Negotiation with the capability
set by AN0 and AN1 pins. When low, this puts the part into Forced Mode with the
capability set by AN0 and AN1 pins.
AN0 / AN1: These input pins control the forced or advertised operating mode of the
DP83848VYB according to the following table. The value on these pins is set by
connecting the input pins to GND (0) or V
should NEVER be connected directly to GND or V
The value set at this input is latched into the DP83848VYB at Hardware-Reset.
The float/pull-down status of these pins are latched into the Basic Mode Control Register
and the Auto_Negotiation Advertisement Register during Hardware-Reset.
The default is 111 since the these pin have internal pull-ups.
MII MODE SELECT: This strapping option pair determines the operating mode of the
MAC Data Interface. Default operation (No pull-ups) will enable normal MII Mode of
operation. Strapping MII_MODE high will cause the device to be in RMII or SNI modes
of operation, determined by the status of the SNI_MODE strap. Since the pins include
internal pull-downs, the default values are 0.
The following table details the configurations:
MII_MODE
AN_EN
AN_EN
0
0
0
0
1
1
1
1
0
1
1
SNI_MODE
10
AN1
AN1
X
0
0
1
1
0
0
1
1
0
1
A 2.2 kΩ resistor should be used for pull-down or pull-up to
change the default strap option. If the default option is re-
quired, then there is no need for external pull-up or pull down
resistors. Since these pins may have alternate functions after
reset is deasserted, they should not be connected directly to
V
CC
or GND.
AN0
AN0
0
1
0
1
0
1
0
1
Description
10BASE-T, Half-Duplex
10BASE-T, Full-Duplex
100BASE-TX, Half-Duplex
100BASE-TX, Full-Duplex
10BASE-T, Half/Full-Duplex
100BASE-TX, Half/Full-Duplex
10BASE-T, Half-Duplex,
100BASE-TX, Half-Duplex
10BASE-T, Half/Full-Duplex,
100BASE-TX, Half/Full-Duplex
CC
(1) through 2.2 kΩ resistors. These pins
MAC Interface Mode
10 Mb SNI Mode
RMII Mode
MII Mode
CC
Advertised Mode
.
Forced Mode