DP83848VYB National Semiconductor, DP83848VYB Datasheet - Page 49

• Manufacturer Part Number: DP83848VYB
• Description: TRANSCEIVER, ENET PHY, 10/100, 48LQFP
• Manufacturer: National Semiconductor

Specifications of DP83848VYB

• Data Rate: 100Mbps
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3u
• Supply Current: 92mA
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +105°C
• Digital Ic Case Style: LQFP
• No.: RoHS Compliant
• Interface Type: MII Serial, RMII
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Not Compliant

15:6
Bit
Bit
1:0
Bit
15
14
3
2
7.2.8 LED Direct Control Register (LEDCR)
This register provides the ability to directly control any or all LED outputs. It does not provide read access to LEDs.
5
4
3
2
1
0
7.2.9 PHY Control Register (PHYCR)
This register provides control for Phy functions such as MDIX, BIST, LED configuration, and Phy address. It also provides Pause
Negotiation status.
ELAST_BUF[1:0]
FORCE_MDIX
DRV_SPDLED
DRV_LNKLED
DRV_ACTLED
RX_OVF_STS
RX_UNF_STS
RESERVED
MDIX_EN
Bit Name
Bit Name
Bit Name
SPDLED
LNKLED
ACTLED
TABLE 28. LED Direct Control Register (LEDCR), address 0x18h
TABLE 29. PHY Control Register (PHYCR), address 0x19h
Strap, RW
Default
Default
01, RW
Default
0, RW
0, RW
0, RW
0, RW
0, RW
0, RW
0, RW
0, RO
0, RO
0, RO
Auto-MDIX Enable:
1 = Enable Auto-neg Auto-MDIX capability.
0 = Disable Auto-neg Auto-MDIX capability.
The Auto-MDIX algorithm requires that the Auto-Negotiation Enable bit in the
BMCR register to be set. If Auto-Negotiation is not enabled, Auto-MDIX should
be disabled as well.
Force MDIX:
1 = Force MDI pairs to cross.
0 = Normal operation.
RX FIFO Over Flow Status:
0 = Normal.
1 = Overflow detected.
RX FIFO Under Flow Status:
0 = Normal.
1 = Underflow detected.
Receive Elasticity Buffer:
This field controls the Receive Elasticity Buffer which allows for frequency
variation tolerance between the 50 MHz RMII clock and the recovered data. The
following values indicate the tolerance in bits for a single packet. The minimum
setting allows for standard Ethernet frame sizes at +/-50ppm accuracy for both
RMII and Receive clocks. For greater frequency tolerance the packet lengths may
be scaled (i.e. for +/-100ppm, the packet lenths need to be divided by 2).
00 = 14 bit tolerance (up to 16800 byte packets)
01 = 2bit tolerance (up to 2400 byte packets)
10 = 6bit tolerance (up to 7200 byte packets)
11 = 10 bit tolerance (up to 12000 byte packets)
RESERVED: Writes ignored, read as 0.
1 = Drive value of SPDLED bit onto LED_SPEED output.
0 = Normal operation.
1 = Drive value of LNKLED bit onto LED_LINK output.
0 = Normal operation.
1 = Drive value of ACTLED bit onto LED_ACT/LED_COL output.
0 = Normal operation.
Value to force on LED_SPEED output.
Value to force on LED_LINK output.
Value to force on LED_ACT/LED_COL output.
(Receive on TPTD pair, Transmit on TPRD pair)
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Description
Description
Description
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