DP83848VYB National Semiconductor, DP83848VYB Datasheet - Page 72
![TRANSCEIVER, ENET PHY, 10/100, 48LQFP](/photos/19/0/190032/ge48lqfp05-40_sml.jpg)
DP83848VYB
Manufacturer Part Number
DP83848VYB
Description
TRANSCEIVER, ENET PHY, 10/100, 48LQFP
Manufacturer
National Semiconductor
Datasheet
1.DP83848VYB.pdf
(76 pages)
Specifications of DP83848VYB
Data Rate
100Mbps
No. Of Ports
1
Ethernet Type
IEEE 802.3u
Supply Current
92mA
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-40°C To +105°C
Digital Ic Case Style
LQFP
No.
RoHS Compliant
Interface Type
MII Serial, RMII
Rohs Compliant
Yes
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DP83848VYB/NOPB
Manufacturer:
NS
Quantity:
570
Company:
Part Number:
DP83848VYB/NOPB
Manufacturer:
Texas Instruments
Quantity:
10 000
www.national.com
T2.27.1
T2.27.2
T2.27.3
T2.27.4
T2.27.5
Parameter
8.2.27 RMII Receive Timing
Note: Per the RMII Specification, output delays assume a 25pF load.
Note: CRS_DV is asserted asynchronously in order to minimize latency of control signals through the Phy. CRS_DV may toggle synchronously at the end of the
Note: RX_DV is synchronous to X1. While not part of the RMII specification, this signal is provided to simplify recovery of receive data.
packet to indicate CRS deassertion.
X1 Clock Period
RXD[1:0], CRS_DV, RX_DV and
RX_ER output delay from X1 rising
CRS ON delay (100Mb)
CRS OFF delay (100Mb)
RXD[1:0] and RX_ER latency
(100Mb)
Description
50 MHz Reference Clock
From JK symbol on PMD
Receive Pair to initial assertion of
CRS_DV
From TR symbol on PMD
Receive Pair to initial deassertion
of CRS_DV
From symbol on Receive Pair.
Elasticity buffer set to default
value (01)
Notes
72
Min
2
18.5
Typ
20
27
38
Max
14
30011746
Units
bits
bits
bits
ns
ns