DP83848VYB National Semiconductor, DP83848VYB Datasheet - Page 25

• Manufacturer Part Number: DP83848VYB
• Description: TRANSCEIVER, ENET PHY, 10/100, 48LQFP
• Manufacturer: National Semiconductor

Specifications of DP83848VYB

• Data Rate: 100Mbps
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3u
• Supply Current: 92mA
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +105°C
• Digital Ic Case Style: LQFP
• No.: RoHS Compliant
• Interface Type: MII Serial, RMII
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Not Compliant

transformers then the droop characteristics of the transform-
ers will dominate resulting in potentially serious BLW.
The digital oscilloscope plot provided in Figure 9 illustrates
the severity of the BLW event that can theoretically be gen-
erated during 100BASE-TX packet transmission. This event
consists of approximately 800 mV of DC offset for a period of
120 ms. Left uncompensated, events such as this can cause
packet loss.
4.2.3 Signal Detect
The signal detect function of the DP83848VYB is incorporat-
ed to meet the specifications mandated by the ANSI FDDI TP-
PMD Standard as well as the IEEE 802.3 100BASE-TX
Standard for both voltage thresholds and timing parameters.
Note that the reception of normal 10BASE-T link pulses and
fast link pulses per IEEE 802.3u Auto-Negotiation by the
100BASE-TX receiver do not cause the DP83848VYB to as-
sert signal detect.
4.2.4 MLT-3 to NRZI Decoder
The DP83848VYB decodes the MLT-3 information from the
Digital Adaptive Equalizer block to binary NRZI data.
4.2.5 NRZI to NRZ
In a typical application, the NRZI to NRZ decoder is required
in order to present NRZ formatted data to the descrambler.
4.2.6 Serial to Parallel
The 100BASE-TX receiver includes a Serial to Parallel con-
verter which supplies 5-bit wide data symbols to the PCS Rx
state machine.
4.2.7 Descrambler
A serial descrambler is used to de-scramble the received NRZ
data. The descrambler has to generate an identical data
scrambling sequence (N) in order to recover the original un-
scrambled data (UD) from the scrambled data (SD) as rep-
resented in the equations:
Synchronization of the descrambler to the original scrambling
sequence (N) is achieved based on the knowledge that the
incoming scrambled data stream consists of scrambled IDLE
data. After the descrambler has recognized 12 consecutive
IDLE code-groups, where an unscrambled IDLE code-group
in 5B NRZ is equal to five consecutive ones (11111), it will
synchronize to the receive data stream and generate un-
scrambled data in the form of unaligned 5B code-groups.
In order to maintain synchronization, the descrambler must
continuously monitor the validity of the unscrambled data that
it generates. To ensure this, a line state monitor and a hold
timer are used to constantly monitor the synchronization sta-
tus. Upon synchronization of the descrambler the hold timer
starts a 722 µs countdown. Upon detection of sufficient IDLE
code-groups (58 bit times) within the 722 µs period, the hold
timer will reset and begin a new countdown. This monitoring
operation will continue indefinitely given a properly operating
network connection with good signal integrity. If the line state
monitor does not recognize sufficient unscrambled IDLE
code-groups within the 722 µs period, the entire descrambler
will be forced out of the current state of synchronization and
reset in order to re-acquire synchronization.
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4.2.8 Code-group Alignment
The code-group alignment module operates on unaligned 5-
bit data from the descrambler (or, if the descrambler is by-
passed, directly from the NRZI/NRZ decoder) and converts it
into 5B code-group data (5 bits). Code-group alignment oc-
curs after the J/K code-group pair is detected. Once the J/K
code-group pair (11000 10001) is detected, subsequent data
is aligned on a fixed boundary.
4.2.9 4B/5B Decoder
The code-group decoder functions as a look up table that
translates incoming 5B code-groups into 4B nibbles. The
code-group decoder first detects the J/K code-group pair pre-
ceded by IDLE code-groups and replaces the J/K with MAC
preamble. Specifically, the J/K 10-bit code-group pair is re-
placed by the nibble pair (0101 0101). All subsequent 5B
code-groups are converted to the corresponding 4B nibbles
for the duration of the entire packet. This conversion ceases
upon the detection of the T/R code-group pair denoting the
End of Stream Delimiter (ESD) or with the reception of a min-
imum of two IDLE code-groups.
4.2.10 100BASE-TX Link Integrity Monitor
The 100 Base TX Link monitor ensures that a valid and stable
link is established before enabling both the Transmit and Re-
ceive PCS layer.
Signal detect must be valid for 395us to allow the link monitor
to enter the 'Link Up' state, and enable the transmit and re-
ceive functions.
4.2.11 Bad SSD Detection
A Bad Start of Stream Delimiter (Bad SSD) is any transition
from consecutive idle code-groups to non-idle code-groups
which is not prefixed by the code-group pair /J/K.
If this condition is detected, the DP83848VYB will assert
RX_ER and present RXD[3:0] = 1110 to the MII for the cycles
that correspond to received 5B code-groups until at least two
IDLE code groups are detected. In addition, the False Carrier
Sense Counter register (FCSCR) will be incremented by one.
Once at least two IDLE code groups are detected, RX_ER
and CRS become de-asserted.
4.3 10BASE-T TRANSCEIVER MODULE
The 10BASE-T Transceiver Module is IEEE 802.3 compliant.
It includes the receiver, transmitter, collision, heartbeat, loop-
back, jabber, and link integrity functions, as defined in the
standard. An external filter is not required on the 10BASE-T
interface since this is integrated inside the DP83848VYB.
This section focuses on the general 10BASE-T system level
operation.
4.3.1 Operational Modes
The DP83848VYB has two basic 10BASE-T operational
modes:
— Half Duplex mode
— Full Duplex mode
Half Duplex Mode
In Half Duplex mode the DP83848VYB functions as a stan-
dard IEEE 802.3 10BASE-T transceiver supporting the CS-
MA/CD protocol.
Full Duplex Mode
In Full Duplex mode the DP83848VYB is capable of simulta-
neously transmitting and receiving without asserting the col-
lision signal. The DP83848VYB's 10 Mb/s ENDEC is
designed to encode and decode simultaneously.
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