DP83848VYB National Semiconductor, DP83848VYB Datasheet - Page 7

• Manufacturer Part Number: DP83848VYB
• Description: TRANSCEIVER, ENET PHY, 10/100, 48LQFP
• Manufacturer: National Semiconductor

Specifications of DP83848VYB

• Data Rate: 100Mbps
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3u
• Supply Current: 92mA
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +105°C
• Digital Ic Case Style: LQFP
• No.: RoHS Compliant
• Interface Type: MII Serial, RMII
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Not Compliant

MDC
MDIO
Signal Name
TX_CLK
TX_EN
TXD_0
TXD_1
TXD_2
TXD_3
RX_CLK
RX_DV
1.0 Pin Descriptions
The DP83848VYB pins are classified into the following inter-
face categories (each interface is described in the sections
that follow):
•
•
•
•
•
•
•
•
•
•
Note: Strapping pin option. Please see Section 1.7 STRAP OPTIONS for
1.1 SERIAL MANAGEMENT INTERFACE
1.2 MAC DATA INTERFACE
Signal
Name
Serial Management Interface
MAC Data Interface
Clock Interface
LED Interface
JTAG Interface
Reset and Power Down
Strap Options
10/100 Mb/s PMD Interface
Special Connect Pins
Power and Ground pins
strap definitions.
S, O, PD
S, I, PD
Type
Type
I, PD
I/O
O
O
I
I
Pin #
Pin #
31
30
38
39
1
2
3
4
5
6
MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/
output serial interface which may be asynchronous to transmit and receive clocks. The
maximum clock rate is 25 MHz with no minimum clock rate.
MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be
sourced by the station management entity or the PHY. This pin requires a 1.5 kΩ pullup resistor.
MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100 Mb/s mode or 2.5 MHz in 10
Mb/s mode derived from the 25 MHz reference clock.
Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference
for both transmit and receive.
SNI TRANSMIT CLOCK: 10 MHz Transmit clock output in 10 Mb SNI mode. The MAC should
source TX_EN and TXD_0 using this clock.
MII TRANSMIT ENABLE: Active high input indicates the presence of valid data inputs on TXD
[3:0].
RMII TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD[1:0].
SNI TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD_0.
MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that accept data synchronous
to the TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode).
RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that accept data synchronous
to the 50 MHz reference clock.
SNI TRANSMIT DATA: Transmit data SNI input pin, TXD_0, that accept data synchronous to
the TX_CLK (10 MHz in 10 Mb/s SNI mode).
MII RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks for 100 Mb/s mode and
2.5 MHz for 10 Mb/s mode.
Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference
for both transmit and receive.
SNI RECEIVE CLOCK: Provides the 10 MHz recovered receive clocks for 10 Mb/s SNI mode.
MII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the
corresponding RXD[3:0]. Mll mode by default with internal pulldown.
RMII Synchronous RECEIVE DATA VALID:This signal provide the RMII Receive Data Valid
indication independent of Carrier Sense.
This pin is not used in SNI mode.
7
All DP83848VYB signal pins are I/O cells regardless of the
particular use. The definitions below define the functionality
of the I/O cells for each pin.
Type: I
Type: O
Type: I/O
Type OD
Type: PD,PU Internal Pulldown/Pullup
Type: S
Description
Description
Input
Output
Input/Output
Open Drain
Strapping Pin (All strap pins have weak
internal pull-ups or pull-downs. If the default
strap value is to be changed then an external
2.2 kΩ resistor should be used. Please see
Section 1.7 STRAP OPTIONS for details.)
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