DP83848VYB National Semiconductor, DP83848VYB Datasheet - Page 37

TRANSCEIVER, ENET PHY, 10/100, 48LQFP

DP83848VYB

Manufacturer Part Number
DP83848VYB
Description
TRANSCEIVER, ENET PHY, 10/100, 48LQFP
Manufacturer
National Semiconductor
Datasheet

Specifications of DP83848VYB

Data Rate
100Mbps
No. Of Ports
1
Ethernet Type
IEEE 802.3u
Supply Current
92mA
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-40°C To +105°C
Digital Ic Case Style
LQFP
No.
RoHS Compliant
Interface Type
MII Serial, RMII
Rohs Compliant
Yes
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DP83848VYB/NOPB
Manufacturer:
NS
Quantity:
570
Part Number:
DP83848VYB/NOPB
Manufacturer:
Texas Instruments
Quantity:
10 000
Part Number:
DP83848VYB/NOPB
0
Bit
15
14
13
12
11
10
7.1.1 Basic Mode Control Register (BMCR)
9
8
AUTO-NEGOTIATION
AUTO-NEGOTIATION
SPEED SELECTION
POWER DOWN
DUPLEX MODE
LOOPBACK
RESTART
Bit Name
ISOLATE
ENABLE
RESET
TABLE 12. Basic Mode Control Register (BMCR), address 0x00h
Strap, RW
Strap, RW
Strap, RW
0, RW/SC
0, RW/SC
Default
0, RW
0, RW
0, RW
Reset:
1 = Initiate software Reset / Reset in Process.
0 = Normal operation.
This bit, which is self-clearing, returns a value of one until the reset process is
complete. The configuration is re-strapped.
Loopback:
1 = Loopback enabled.
0 = Normal operation.
The loopback function enables MII transmit data to be routed to the MII receive data
path.
Setting this bit may cause the descrambler to lose synchronization and produce a 500
µs “dead time” before any valid data will appear at the MII receive outputs.
Speed Select:
When auto-negotiation is disabled writing to this bit allows the port speed to be
selected.
1 = 100 Mb/s.
0 = 10 Mb/s.
Auto-Negotiation Enable:
Strap controls initial value at reset.
If FX is enabled (FX_EN = 1), then this bit will be reset to 0.
1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are ignored when this bit
is set.
0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port speed and duplex
mode.
Power Down:
1 = Power down.
0 = Normal operation.
Setting this bit powers down the PHY. Only the register block is enabled during a
power down condition. This bit is ORd with the input from the PWRDOWN_INT pin.
When the active low PWRDOWN_INT pin is asserted, this bit will be set.
Isolate:
1 = Isolates the Port from the MII with the exception of the serial management.
0 = Normal operation.
Restart Auto-Negotiation:
1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation process. If Auto-
Negotiation is disabled (bit 12 = 0), this bit is ignored. This bit is self-clearing and will
return a value of 1 until Auto-Negotiation is initiated, whereupon it will self-clear.
Operation of the Auto-Negotiation process is not affected by the management entity
clearing this bit.
0 = Normal operation.
Duplex Mode:
When auto-negotiation is disabled writing to this bit allows the port Duplex capability
to be selected.
1 = Full Duplex operation.
0 = Half Duplex operation.
37
Description
www.national.com

Related parts for DP83848VYB