M52S128168A-7.5BG ELITE SEMICONDUCTOR, M52S128168A-7.5BG Datasheet - Page 17

• Manufacturer Part Number: M52S128168A-7.5BG
• Description: DRAM IC
• Manufacturer: ELITE SEMICONDUCTOR

Specifications of M52S128168A-7.5BG

• Ic Interface Type: Parallel
• Frequency: 133MHz
• Termination Type: SMD
• Supply Voltage Max: 2.7V
• Memory Voltage, Vcc: 2.5 V
• Interface Type: Parallel
• Memory Size: 128Mbit
• Supply Voltage Min: 2.3V
• Operating Temperature Min: 0��C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Operating Temperature Max: 70°C
• Page Size: 128MB
• Memory Case Style: FBGA
• No. Of Pins: 54
• Operating Temperature Range: 0°C To +70°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ESMT
CBR (auto) refresh command
generated internally.
activate command.
cannot accept any other command.
Self refresh entry command
When CKE goes to high, the DRAM exits the self refresh mode.
so there is no need for external control.
Before executing self refresh, all banks must be precharged.
Burst stop command
This command terminates the current burst operation.
Burst stop is valid at every burst length.
Elite Semiconductor Memory Technology Inc.
This command is a request to begin the CBR refresh operation. The refresh address is
Before executing CBR refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (precharged) state and ready for a row
During t
After the command execution, self refresh operation continues while CKE remains low.
During self refresh mode, refresh interval and refresh operation are performed internally,
( CS , RAS , CAS = Low, WE , CKE = High)
( CS , RAS , CAS , CKE = Low , WE = High)
( CS , WE = Low, RAS , CAS = High)
RC
period (from refresh command to refresh or activate command), the DRAM
Publication Date: Oct. 2007
Revision: 1.1
M52S128168A
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